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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet
Product Features
High Performance Read-While-Write/Erase -- Burst frequency at 66 MHz -- 60 ns Initial Access Read Speed -- 11 ns Burst-Mode Read Speed -- 20 ns Page-Mode Read Speed -- 4-, 8-, 16-, and Continuous-Word Burst Mode Reads -- Burst and Page Mode Reads in all Blocks, across all partition boundaries -- Burst Suspend Feature -- Enhanced Factory Programming at 3.1 s/word (typ. for 0.13 m) Architecture -- Multiple 4 Mbit Partitions -- Dual Operation: Read-while-Write and Read-while-Erase -- 8 KB parameter blocks -- 64 KB main blocks -- Top or Bottom Parameter Configurations -- 16 bit wide data bus -- Multiplexed Address data bus Power -- VCC = 1.70 V to 1.95 V -- VCCQ = 1.70 V to 2.24 V or 1.35 V to 1.80 V -- Standby current (0.13 m): 8 A (typ.) -- Read current: 7 mA (typ.) Security -- 128 bit Protection Register -- 64 Unique Bits Programmed by Numonyx -- 64 User-Programmable Bits -- Absolute Write Protection with VPP at Ground -- Individual and Instantaneous Block Locking/Unlocking with Lock-Down Capability Software -- 5 s (typ.) Program and Erase Suspend Latency Time -- NumonyxTM Flash Data Integrator (NumonyxTM FDI) and Common Flash Interface Compatible -- Programmable WAIT Signal Polarity Quality and Reliability -- Temperature Range: -40 C to +85 C -- 100k Erase Cycles per Block -- 130 nm ETOXTM VIII Process -- 90 nm ETOXTM IX Process -- Density and Package Ballout -- 130 nm: 32-, 64-, and 128-Mbit -- 90 nm: 32-, 64-Mbit -- 44-ball VF BGA -- 88-ball QUAD+
Order Number: 313272-06 November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal L ines and D isc laim er s
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2007, Numonyx B.V., All Rights Reserved.
Datasheet 2
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Contents
1.0 Introduction .............................................................................................................. 6 1.1 Document Purpose .............................................................................................. 6 1.2 Nomenclature ..................................................................................................... 6 1.3 Conventions ....................................................................................................... 6 Functional Overview .................................................................................................. 8 2.1 Memory Map and Partitioning ................................................................................ 9 Package Information ............................................................................................... 12 Ballout and Signal Descriptions ............................................................................... 14 4.1 Ballouts ........................................................................................................... 14 4.2 Signal Descriptions ............................................................................................ 15 Maximum Ratings and Operating Conditions............................................................ 20 5.1 Absolute Maximum Ratings................................................................................. 20 5.2 Operating Conditions ......................................................................................... 20 Electrical Specifications ........................................................................................... 21 6.1 DC Current Characteristics.................................................................................. 21 6.2 DC Voltage Characteristics.................................................................................. 22 AC Characteristics ................................................................................................... 24 7.1 AC I/O Test Conditions....................................................................................... 24 7.2 Device Capacitance ........................................................................................... 24 7.3 AC Read Characteristics, AD-Mux ........................................................................ 25 7.4 AC Write Characteristics, AD-Mux ........................................................................ 32 7.5 Program and Erase Characteristics....................................................................... 34 7.6 Reset Specifications........................................................................................... 35 Power and Reset Specifications ............................................................................... 37 8.1 Active Power..................................................................................................... 37 8.2 Automatic Power Savings ................................................................................... 37 8.3 Standby Power.................................................................................................. 37 8.4 Power-Up/Down Characteristics........................................................................... 37 8.4.1 System Reset and RST#.......................................................................... 37 8.4.2 VCC, VPP, and RST# Transitions............................................................... 38 8.5 Power Supply Decoupling ................................................................................... 38 Device Operations ................................................................................................... 39 9.1 Bus Operations ................................................................................................. 39 9.1.1 Read .................................................................................................... 39 9.1.2 Burst Suspend ....................................................................................... 40 9.1.3 Standby ................................................................................................ 40 9.1.4 Reset.................................................................................................... 40 9.1.5 Write .................................................................................................... 41 9.2 Device Commands............................................................................................. 41 9.3 Command Sequencing ....................................................................................... 44 Operations ...................................................................................................... 45 Read Array ....................................................................................................... 45 Read Device ID ................................................................................................. 45 Read Query (CFI) .............................................................................................. 46 Read Status Register ......................................................................................... 46 Clear Status Register ......................................................................................... 47
2.0 3.0 4.0
5.0
6.0
7.0
8.0
9.0
10.0 Read 10.1 10.2 10.3 10.4 10.5
November 2007 Order Number: 313272-06
Datasheet 3
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
11.0 Program Operations .................................................................................................48 11.1 Word Program ...................................................................................................48 11.2 Factory Programming .........................................................................................49 11.3 Enhanced Factory Program (EFP) .........................................................................50 11.3.1 EFP Requirements and Considerations .......................................................50 11.3.2 Setup....................................................................................................51 11.3.3 Program ................................................................................................51 11.3.4 Verify....................................................................................................51 11.3.5 Exit.......................................................................................................52 12.0 Program and Erase Operations.................................................................................53 12.1 Program/Erase Suspend and Resume ...................................................................53 12.2 Block Erase .......................................................................................................55 12.3 Read-While-Write and Read-While-Erase ...............................................................57 13.0 Security Modes ........................................................................................................59 13.1 Block Lock Operations ........................................................................................59 13.1.1 Lock......................................................................................................60 13.1.2 Unlock...................................................................................................60 13.1.3 Lock-Down ............................................................................................60 13.1.4 Block Lock Status ...................................................................................61 13.1.5 Lock During Erase Suspend ......................................................................61 13.1.6 Status Register Error Checking .................................................................61 13.1.7 WP# Lock-Down Control ..........................................................................62 13.2 Protection Register.............................................................................................62 13.2.1 Reading the Protection Register ................................................................63 13.2.2 Programing the Protection Register ...........................................................63 13.2.3 Locking the Protection Register.................................................................63 13.3 VPP Protection ...................................................................................................65 14.0 Set Configuration Register .......................................................................................66 14.1 Read Mode (CR[15]) ..........................................................................................67 14.2 First Access Latency Count (CR[13:11]) ................................................................67 14.2.1 Latency Count Settings............................................................................68 14.3 WAIT Signal Polarity (CR[10]) .............................................................................68 14.4 WAIT Signal Function .........................................................................................68 14.5 Data Hold (CR[9])..............................................................................................69 14.6 WAIT Delay (CR[8]) ...........................................................................................70 14.7 Burst Sequence (CR[7])......................................................................................70 14.8 Clock Edge (CR[6]) ............................................................................................71 14.9 Burst Wrap (CR[3])............................................................................................71 14.10 Burst Length (CR[2:0]).......................................................................................72 15.0 Write State Machine States ......................................................................................73 16.0 Common Flash Interface ..........................................................................................76 16.1 Query Structure Output ......................................................................................76 16.2 Query Structure Overview...................................................................................77 16.3 Block Status Register .........................................................................................77 16.4 CFI Query Identification String ............................................................................78 16.5 Device Geometry Definition .................................................................................80 16.6 Numonyx-Specific Extended Query Table ..............................................................81 A Ordering Information ...............................................................................................87
Datasheet 4
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Revision History
Date June 2006 July 2006
Revision 001 002 Initial Release. Made minor formatting changes.
Description
December 2006
003
Changed Burst Frequency from 54 MHz to 66 MHz and Burst Mode Read speed from 14 ns to 11 ns per specification improvements. Removed 80 ns and extended voltage range (1.35-1.8) I/O specifications because feature is no longer supported. Added the 44 Ball VF BGA package and ballouts and line items. Updated ordering information: HR28F320W18BE Updated ordering information. Applied Numonyx branding.
February 2007 August 2007 November 2007
004 005 06
November 2007 Order Number: 313272-06
Datasheet 5
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
1.0
Introduction
The NumonyxTM Wireless Flash Memory device provides high-performance asynchronous and synchronous burst reads, ideal for low-voltage burst CPUs. Combining high read performance with flash memory's intrinsic non-volatility, the W18 device reduces the total memory requirement while increasing reliability and reducing overall system power consumption and cost. Its flexible, multi-partition architecture allows programming or erasing to occur in one partition while reading from another partition, providing higher data write throughput compared to single partition architectures. The dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. The designer can also choose the size of the code and data partitions via the flexible multipartition architecture.
1.1
Document Purpose
This datasheet contains information about the NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO device family.
1.2
Nomenclature
Many acronyms that describe product features or usage are defined as follows:
APS BBA CFI CUI EFP FDI NC OTP PBA RWE RWW SCSP SRD WSM
Automatic Power Savings Block Base Address Common Flash Interface Command User Interface Enhanced Factory Programming Flash Data Integrator No Connect One-Time Programmable Partition Base Address Read-While-Erase Read-While-Write Quad ballout Status Register Data Write State Machine
1.3
Conventions
The following abbreviated terms and phrases are used throughout this document:
1.8 V Set Clear Pin Signal Word Signal Names
Refers to the full VCC voltage range of 1.7 V - 1.95 V (except where noted) and "VPP = 12 V" refers to 12 V 5%. When referring to registers, the term set means the bit is a logical 1, and clear means the bit is a logical 0. The terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (ball is the term used for SCSP). 2 bytes or 16 bits. All CAPS
Datasheet 6
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Voltage
Voltage applied to the signal is subscripted, for example, VPP.
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these references, the following conventions have been adopted: Block Main block Parameter Block Block Base Address (BBA) Partition Partition Base Address (PBA) Top Partition Bottom Partition Main Partition Parameter Partition Top Parameter Device (TPD) A group of bits (or words) that erase simultaneously with one block erase instruction. Contains 32 Kwords. Contains 4 Kwords. The first address of a block. A group of blocks that share erase and program circuitry and a common status register. The first address of a partition. For example, on a 32-Mbit top-parameter device, partition number 5 has a PBA of 140000h. Located at the highest physical device address. This partition may be a main partition or a parameter partition. Located at the lowest physical device address. This partition may be a main partition or a parameter partition. Contains only the main blocks. Contains a mixture of main blocks and parameter blocks. TPD has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. This was formerly referred to as top-boot flash device. BPD has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of that partition. This was formerly referred to as bottom-boot flash device.
Bottom Parameter Device (BPD)
November 2007 Order Number: 313272-06
Datasheet 7
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
2.0
Functional Overview
This section provides an overview of the NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO device features, packaging, signal naming, and device architecture. The W18 device provides Read-While-Write (RWW) and Read-While-Erase (RWE) capability with high-performance synchronous and asynchronous reads on packagecompatible densities with a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks. The memory architecture for the W18 device consists of multiple 4 Mbit partitions, the exact number depending on device density. By dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. Burst reads can traverse partition boundaries, but the user application code is responsible for ensuring that they do not extend into a partition that is actively programming or erasing. Although each partition has burst read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. A program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. After device power-up or reset, the W18 device defaults to asynchronous read configuration. Writing to the device's configuration register enables synchronous burstmode read operation. In synchronous mode, the CLK input increments an internal burst address generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when data from the flash memory device is ready. In addition to its improved architecture and interface, the W18 device incorporates Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power designs. The EFP feature provides the fastest currently-available program performance, which can increase a factory's manufacturing throughput. The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V. With the 1.8 V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In addition to voltage flexibility, the dedicated VPP input provides complete data protection when VPP VPPLK. A 128-bit protection register enhances the user's ability to implement new security techniques and data protection schemes. Unique flash device identification and fraud-, cloning-, or content- protection schemes are possible through a combination of factoryprogrammed and user-OTP data cells. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. An additional block lock-down capability provides hardware protection where software commands alone cannot change the block's protection status. The W18 device Command User Interface (CUI) is the system processor's link to internal flash memory operation. A valid command sequence written to the CUI initiates device Write State Machine (WSM) operation that automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. An internal status register provides ready/busy indication results of the operation (success, fail, and so on).
Datasheet 8
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Three power-saving features, Automatic Power Savings (APS), standby, and RST#, can significantly reduce power consumption. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also resets the part to read-array mode (important for systemlevel reset), clears internal status registers, and provides an additional level of flash write protection.
2.1
Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or RWE operations and allows users to segment code and data areas on 4 Mbit boundaries. The device's memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. Each block can be erased independently in block erase mode. Simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. See Table 1, "Bottom Parameter Memory Map" on page 10 and Table 2, "Top Parameter Memory Map" on page 11. The 32-Mbit device has eight partitions; the 64-Mbit device has 16 partitions, and the 128-Mbit device has 32 partitions. Each device density contains one parameter partition and several main partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each. The bulk of the array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
November 2007 Order Number: 313272-06
Datasheet 9
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
.
Table 1:
Bottom Parameter Memory Map
Size (KW) Blk # 32 Mbit Blk # 64 Mbit Blk # 262 .. 128 Mbit 7F8000-7FFFFF .. 400000-407FFF 3F8000-3FFFFF .. 200000-207FFF 1F8000-1FFFFF .. 100000-107FFF 0F8000-0FFFFF .. 0C0000-0C7FFF 0B8000-0BFFFF .. 080000-087FFF 078000-07FFFF .. 040000-047FFF 038000-03FFFF .. 008000-00FFFF 007000-007FFF .. 000000-000FFF
Sixteen Partitions
32 .. 32
135
Eight Partitions
32 ..
134 ..
3F8000-3FFFFF ..
134 .. 71 70 .. 39 38 .. 31 30 .. 23 22 .. 15 14 .. 8 7 .. 0
32
71
200000-207FFF
Four Partitions
32 ..
70 ..
1F8000-1FFFFF ..
70 ..
1F8000-1FFFFF .. 100000-107FFF 0F8000-0FFFFF .. 0C0000-0C7FFF 0B8000-0BFFFF .. 080000-087FFF 078000-07FFFF .. 040000-047FFF 038000-03FFFF .. 008000-00FFFF 007000-007FFF .. 000000-000FFF
Main Partitions
32
39
100000-107FFF
39
One Partition
32 ..
38 ..
0F8000-0FFFFF ..
38 .. 31 30 .. 23 22 .. 15 14 .. 8 7 .. 0
32
31
0C0000-0C7FFF
One Partition
32 ..
30 ..
0B8000-0BFFFF .. 080000-087FFF 078000-07FFFF .. 040000-047FFF 038000-03FFFF .. 008000-00FFFF 007000-007FFF .. 000000-000FFF
32
23
One Partition
32 ..
22 .. 15 14 .. 8 7 .. 0
32
Parameter Partition
32 .. One Partition 32 4 .. 4
128 Mbit is not available at 90 nm.
Datasheet 10
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 2:
Top Parameter Memory Map
Size (KW) 4 .. Blk # 70 .. 32 Mbit 1FF000-1FFFFF .. Blk # 134 .. 64 Mbit 3FF000-3FFFFF .. Blk # 262 .. 128 Mbit 7FF000-7FFFFF .. 7F8000-7F8FFF 7F0000-7F7FFF .. 7C0000-7C7FFF 7B8000-7BFFFF .. 780000-787FFF 778000-77FFFF .. 740000-747FFF 738000-73FFFF .. 700000-707FFF 6F8000-6FFFFF .. 600000-607FFF 5F8000-5FFFFF .. 400000-407FFF 3F8000-3FFFFF .. 000000-007FFF Datasheet 11
Parameter Partition
One Partition
4 32 ..
63 62 ..
1F8000-1F8FFF 1F0000-1F7FFF ..
127 126 ..
3F8000-3F8FFF 3F0000-3F7FFF ..
255 254 .. 248 247 .. 240 239 .. 232 231 .. 224 223 .. 192 191 .. 128 127 .. 0
32
56
1C0000-1C7FFF
120
3C0000-3C7FFF
One Partition
32 ..
55 ..
1B8000-1BFFFF ..
119 ..
3B8000-3BFFFF .. 380000-387FFF 378000-37FFFF .. 340000-347FFF 338000-33FFFF .. 300000-307FFF 2F8000-2FFFFF .. 200000-207FFF 1F8000-1FFFFF .. 000000-007FFF
32
48
18000-187FFF
112
One Partition
32 ..
47 ..
178000-17FFFF ..
111 .. 104 103 .. 96 95 .. 64 63 .. 0
32
40
140000-147FFF
One Partition
32 ..
39 ..
138000-13FFFF .. 100000-107FFF 0F8000-0FFFFF .. 000000-007FFF
Main Partitions
32
32
Four Partitions
32 ..
31 .. 0
32
Eight Partitions Sixteen Partitions Note:
32 .. 32 32 .. 32
128 Mbit is not available at 90 nm.
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
3.0
Package Information
* Figure 1, "88-ball QUAD+ Ballout (8x10x1.2 mm) Package and Dimensions" * Figure 2, "44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package" and Table 3, "44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package Dimensions"
Figure 1:
88-ball QUAD+ Ballout (8x10x1.2 mm) Package and Dimensions
A 1 Index M a rk
1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E e 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M S1
T o p V ie w - B a ll D o w n
A2 A1
B o t t o m V ie w - B a ll Up
A
Y
D r a w in g n o t to s c a le .
D i m e n s io n s Pa c k a g e H e ig h t Ba ll H e ig h t Pa c k a g e B o d y T h ic k n e s s Ba ll (L e a d ) W id th Pa c k a g e B o d y L e n g th Pa c k a g e B o d y W id th Pitc h Ba ll (L e a d ) C o u n t Se a tin g P la n e C o p la n a rity Co r n e r t o B a ll A 1 D is ta n c e A lo n g E Co r n e r t o B a ll A 1 D is ta n c e A lo n g D
S y m bo l A A1 A2 b D E e N Y S1 S2
Min 0 .2 0 0 0 .3 2 5 9 .9 0 0 7 .9 0 0
M il li m e te r s N om M ax 1 .2 0 0 0 .8 6 0 0 .3 7 5 1 0 .0 0 0 8 .0 0 0 0 .8 0 0 88 1 .2 0 0 0 .6 0 0
Notes
M in 0 .0 0 7 9
Inc h e s N om
M ax 0 .0 4 7 2
0 .4 2 5 1 0 .1 0 0 8 .1 0 0
0 .0 1 2 8 0 .3 8 9 8 0 .3 1 1 0
0 .0 3 3 9 0 .0 1 4 8 0 .3 9 3 7 0 .3 1 5 0 0 .0 3 1 5 88 0 .0 4 7 2 0 .0 2 3 6
0 .0 1 6 7 0 .3 9 7 6 0 .3 1 8 9
1 .1 0 0 0 .5 0 0
0 .1 0 0 1 .3 0 0 0 .7 0 0
0 .0 4 3 3 0 .0 1 9 7
0 .0 0 3 9 0 .0 5 1 2 0 .0 2 7 6
Datasheet 12
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 2:
44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package
Pin 1 Corner
D
S1
Pin 1 Co rn er
S2
1 A B C E D E F G H b
Su pport Sol der Bal ls
2
3
4
5
6
7
8
9
10 1 1 12
13
14
14
13
12
11 1 0
9
8
7
6
5
4
3
2
1 A B C
e
D E F G H
T op View - Plastic Backside
A1 A2 A
Bottom View - Ball Side Up
Seating Plan e
Y
Note: Drawing not to Scale
Table 3:
44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package Dimensions
Millimeters Symbol Min 0.150 0.259 7.600 6.100 0.500 1.250 Nom 0.665 0.309 7.700 6.200 0.500 44 0.600 1.350 Max 1.000 0.359 7.800 6.300 0.080 0.700 1.450 Min 0.0059 0.0102 0.2992 0.2402 0.0197 0.0492 Inches Nom 0.0262 0.0122 0.3031 0.2441 0.0197 44 0.0236 0.0531 Max 0.0394 0.0141 0.3071 0.2480 0.0031 0.0276 0.0571
Package Height Ball Height Package Body T hickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E
A A1 A2 b D E [e] N Y S1 S2
November 2007 Order Number: 313272-06
Datasheet 13
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
4.0
4.1
Ballout and Signal Descriptions
Ballouts
* Figure 3, "QUAD+ Ballout" * Figure 4, "40-Ball VF BGA Ballout"
Figure 3:
QUAD+ Ballout
Pin 1
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
A
B
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
A2
A7
A25
F-WP#
ADV#
A20
A10
A15
E
F
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
S-CS1#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Legend: Active Signals De-Populated Balls Do Not Use
Datasheet 14
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 4:
40-Ball VF BGA Ballout
1 A
W A IT
2
6 4 - M b it A21
3
VSS 3 2 -M b it
4
CLK
5
VCC
6
WE#
7
VPP
8
A19
9
A17
10
NC
B
VCCQ
A16
A 20
ADV#
NC
RST#
W P#
A18
CE#
VSSQ
C
VSS
A /D Q 7
A /D Q 6
A /D Q 1 3
A /D Q 1 2
A /D Q 3
A /D Q 2
A /D Q 9
A /D Q 8
O E#
D
A /D Q 1 5
A /D Q 1 4
VSSQ
A /D Q 5
A /D Q 4
A /D Q 1 1
A /D Q 1 0
VCCQ
A /D Q 1
A /D Q 0
T o p V ie w -- B a ll s id e D o w n
10 A
NC
9
A17
8
A 19
7
VPP
6
W E#
5
VCC
4
C LK
3
VSS 3 2 -M b it
2
6 4 - M b it A21
1
W A IT
B
VSSQ
CE#
A 18
WP#
RST#
NC
ADV#
A20
A16
VCCQ
C
O E#
A /D Q 8
A /D Q 9
A /D Q 2
A /D Q 3
A /D Q 1 2
A /D Q 1 3
A /D Q 6
A /D Q 7
VSS
D
A /D Q 0
A /D Q 1
VCCQ
A /D Q 1 0
A /D Q 1 1
A /D Q 4
A /D Q 5
VSSQ
A /D Q 1 4
A /D Q 1 5
B o tto m V ie w -- B a ll s id e U p
4.2
Signal Descriptions
* Table 4, "Signal Descriptions, QUAD+ Ballout" * Table 5, "Signal Descriptions"
November 2007 Order Number: 313272-06
Datasheet 15
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 4:
Symbol
Signal Descriptions, QUAD+ Ballout (Sheet 1 of 3)
Type Signal Descriptions Notes
Address and Data Signals, A/D-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. * 128-Mbit: AMAX = A22 * 64-Mbit: AMAX = A21 * 32-Mbit: AMAX = A20 * A0 is the lowest-order word address. * Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: A/D-Mux I/O flash signals. During A/D-Mux Read cycles, DQ[15:0] are used to input the lower address followed by readdata output. During A/D-Mux Write cycles, DQ[15:0] are used to input the lower address followed by commands or data. * DQ[15:0] are High-Z when the device is deselected or its output is disabled. * DQ[15:0] is only used with A/D-Mux I/O flash device.
A[MAX:16]
Input
A/DQ[15:0]
Input / Output
1
Control Signals ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. * During a synchronous flash Read operation, the address is latched on the rising edge of ADV# or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or continuously flows through while ADV# is low. * During synchronous PSRAM read and synchronous write modes, the address is either latched on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to latch the address, but can be held low for the entire operation as well. Note: During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
ADV#
Input
F[3:1]-CE#
Input
FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. * F1-CE# is dedicated to flash die #1. * F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. CLOCK: Flash- and Synchronous PSRAM-specific input signal. CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous operations. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. * F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly recommended to always common F1-OE# and F2-OE# on the PCB. RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# disables the output drivers of the selected memory die and places the output drivers in High-Z. If device not present, treat as RFU. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation.
CLK
Input
F[2:1]-OE#
Input
R-OE#
Input
2
F-RST#
Input
Datasheet 16
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 4:
Symbol
Signal Descriptions, QUAD+ Ballout (Sheet 2 of 3)
Type Signal Descriptions WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. * WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable is low. * WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable is high. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-WE# enables Write operations for the selected memory die. Data is latched on the rising edge of R-WE#. If device not present, treat as RFU. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. * F-WP1# is dedicated to flash die #1. * F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU. PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input. When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input. When low, P-MODE# enables access to the configuration register, and to enter or exit LowPower mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM CHIP SELECT: PSRAM-specific signal; low-true input. When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT outputs are placed in a High-Z state. * P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU. * P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or S-CS2 is deasserted, the SRAM die is deselected. * S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as RFU. RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs. When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not present, treat as RFU./ Notes
WAIT
Output
F-WE#
Input
R-WE#
Input
2
F-WP#
Input
P-CRE
Input
3
P-MODE#
Input
3
P[2:1]-CS#
Input
S-CS1# S-CS2
Input
2
R-UB# R-LB#
Input
2
Power Signals F-VPP Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. F[2:1]-VCC supplies the core power to the flash die. F2-VCC is recommended to be tied to F1-VCC, else it is an RFU. I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC supplies the core power to the PSRAM die. If PSRAM not present, treat as RFU. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. If SRAM not present, treat as RFU. 2 2
F[2:1]-VCC
Power
VCCQ P-VCC S-VCC
Power Power Power
November 2007 Order Number: 313272-06
Datasheet 17
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 4:
Symbol VSS
Signal Descriptions, QUAD+ Ballout (Sheet 3 of 3)
Type Groun d -- Signal Descriptions DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: This ball should not be connected to any power supplies, signals, or other balls. This ball can be left floating. RESERVED for FUTURE USE: Reserved by Numonyx for future device functionality and enhancement. This ball must be left floating. Notes
DU
RFU
--
Notes: 1. Only used when A/D-Mux I/O flash is present. 2. Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise treated as RFU. 3. P-CRE and P-MODE# share the same package ball at location K8. Only one signal function is available, depending on the stacked device combination.
Table 5:
Symbol A[21:16]
Signal Descriptions
Type Input Input/ Output Name and Function ADDRESS INPUTS: for memory addresses. 32 Mbit: A[20:16]; 64 Mbit: A[21:16]. ADDRESS/DATA INPUT/OUTPUTS: * Multiplexed address/data pins act as address inputs while ADV# is low. * Addresses are internally latched when ADV# goes high; these signals then become data inputs/ outputs. ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous read operations, all addresses are latched on the ADV# rising edge or on the CLK rising (or falling) edge, whichever occurs first. CHIP ENABLE: * CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. * CE#-high deselects the device, places it in standby state, and places data and WAIT outputs at High-Z. CLOCK: CLK synchronizes the device to the bus frequency in synchronous-read configuration, and increments an internal burst address generator. During synchronous read operations, addresses are latched on the ADV# rising edge or on the CLK rising (or falling) edge, whichever occurs first. OUTPUT ENABLE: Active low OE# enables the device's output data buffers during a read cycle. With OE# at VIH, the device data outputs are placed in a High-Z state. RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides data protection during power transitions. De-asserting RST# enables normal operation and places the flash device in asynchronous read array mode. WAIT: The WAIT signal indicates valid data during synchronous read modes. This signal can be configured to be active-high or active-low based on bit 10 of the Configuration Register. WAIT is tristated if CE# is deasserted. WAIT is not gated by OE#. WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the WE# rising edge. WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See Section 13.1, "Block Lock Operations" on page 59 for details about block locking. Erase and Program Power: A valid voltage on this pin allows erase or programming. Memory contents cannot be altered when VPP < VPPLK . Do not attempt block erase and program operations at invalid VPP voltages. Set VPP = VCC for in-circuit program and erase operations. To accommodate resistor or diode drops, the VIH level of VPP can be as low as VPP1 (min). VPP must remain above VPP1 min to perform in-circuit flash array modification. VPP can be 0 V during read operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles maximum. VPP can be connected to VPP2 for a cumulative total not to exceed 80 hours maximum. Extended use of this pin at VPP2 might reduce block cycling capability.
A/D[15:0]
ADV#
Input
CE#
Input
CLK
Input
OE#
Input
RST#
Input
WAIT
Output
WE#
Input
WP#
Input
VPP
Power
Datasheet 18
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 5:
Symbol VCC VCCQ VSS VSSQ DU
Signal Descriptions
Type Power Power Power Power -- Name and Function Device Power Supply: Writes are inhibited at VCC < VLKO. Do not attempt flash device operations at invalid VCC voltages. Output Power Supply: Enables all outputs to be driven at VCCQ. This input can be tied directly to VCC. Ground: Pins for all internal device circuitry; must be connected to ground. Output Ground: Provides ground to all outputs which are driven by VCCQ. This signal can be tied directly to VSS. Do Not Use: Do not use this pin. Do not connect this pin to any power supplies, signals, or other pins. This pin must be floated.
November 2007 Order Number: 313272-06
Datasheet 19
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
5.0
5.1
Warning: Table 6:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Absolute Maximum Ratings
Parameter Maximum Rating -40 C to +85 C -65 C to +125 C Notes -- -- -- 1,2,3 1 4
Temperature under Bias Storage Temperature Voltage on Any Pin (except VCC, VCCQ, VPP) VPP Voltage VCC and VCCQ Voltage Output Short Circuit Current
-0.5 V to +2.45 V
-0.2 V to +14 V -0.2 V to +2.45 V 100 mA
Notes: 1. All specified voltages are relative to VSS. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 3. VPP program voltage is normally VPP1. VPP can be 12 V 0.6 V for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. Output shorted for no more than one second. No more than one output shorted at a time.
5.2
Warning: Table 7:
Symbol TA VCC VCCQ VPP1 VPP2 tPPH Block Erase Cycles
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Extended Temperature Operation
Parameter1 Operating Temperature VCC Supply Voltage I/O Supply Voltage VPP Voltage Supply (Logic Level) Factory Programming VPP Maximum VPP Hours Main and Parameter Blocks Main Blocks Parameter Blocks VPP = 12 V VPP VCC VPP = 12 V VPP = 12 V Min -40 1.7 1.7 0.90 11.4 -- 100,000 -- -- Nom 25 1.8 1.8 1.80 12.0 -- -- -- -- Max 85 1.95 2.24 1.95 12.6 80 -- 1000 2500 Cycles Unit C V V V V Hours Notes -- 2 2 1 1 1 1 1 1
Notes: 1. VPP is normally VPP1. VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 2. Contact your Numonyx field representative for VCC/VCCQ operations down to 1.65 V.
Datasheet 20
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
6.0
6.1
Note:
Electrical Specifications
DC Current Characteristics
Specifications are for 130 nm and 90 nm devices unless otherwise stated; the 128 Mbit density is supported ONLY on 90 nm.
Table 8:
DC Current Characteristics (Sheet 1 of 2)
VCCQ = 1.8 V
Symbol
Parameter
(1)
32/64-Mbit Typ Max 1
128-Mbit Typ -- Max 1
Unit
Test Condition
Note
ILI
Input Load
--
A
VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQ Max CE# = VCC RST# =VCCQ VCC = VCCMax VCCQ = VCCQ Max CE# = VSSQ RST# =VCCQ All other inputs =VCCQ or VSSQ 4 Word Read Burst length = 4 Burst length = 8 Burst length =16 Burst length = Continuous Burst length = 4 Burst length = 8 Burst length = 16 Burst length = Continuous Burst length = 4 Burst length = 8 Burst length = 16 Burst length = Continuous
8
ILO 130 nm ICCS 90 nm ICCS 130 nm ICCAPS 90 nm ICCAPS
Output Leakage
D[15:0]
--
1
--
1
A
--
8 VCC Standby 22 8 APS 22 Asynchronous Page Mode f=13 MHz
50 50 50 50
8
70 A
9
8
70 A
10
3 6
6 13 14 18 20 16 18 22 25 17 20 25 30 40 15 40
4 6 8 11 11 7 10 12 13 -- -- -- -- 18 8 18
7 13 14 19 20 16 18 22 25 -- -- -- -- 40 15 40
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
3
ICCR
Average VCC Read
Synchronous CLK = 40 MHz
8 10 11 7
3
Synchronous CLK = 54 MHz
10 12 13 8
3
ICCR
Average VCC Read
Synchronous CLK = 66 MHz
11 14 16
3, 4
ICCW
VCC Program
18 8 18
VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP = VPP1, Block Erase in Progress VPP = VPP2, Block Erase in Progress
4,5,6
ICCE
VCC Block Erase 8 15 8 15 mA
4,5,6
November 2007 Order Number: 313272-06
Datasheet 21
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 8:
DC Current Characteristics (Sheet 2 of 2)
VCCQ = 1.8 V
Symbol
Parameter
(1)
32/64-Mbit Typ Max 50 50 50 50
128-Mbit Typ 5 Max 25
Unit
Test Condition
Note
130nm ICCWS 90nm ICCWS 130nm ICCES 90nm ICCWS IPPS (IPPWS, IPPES) IPPR IPPW
8 VCC Program Suspend 22 8 VCC Erase Suspend 22 VPP Standby VPP Program Suspend VPP Erase Suspend VPP Read VPP Program
A A
CE# = VCC, Program Suspended
7
5
25
A A
CE# = VCC, Erase Suspended
7
0.2 2 0.05 8 0.05 8
5 15 0.10 22 0.10 22
0.2 2 0.05 16 0.05 8
5 15 0.10 37 0.10 22
A A mA
VPP 4 -- 5
VPP VCC
VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP = VPP1, Erase in Progress VPP = VPP2, Erase in Progress
IPPE
VPP Erase
mA
5
Notes: 1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25 C. 2. VCCQ = 1.35 V - 1.8V is available on 130 nm products only. 3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ specification for details. 4. Sampled, not 100% tested. 5. VCC read + program current is the sum of VCC read and VCC program currents. 6. VCC read + erase current is the sum of VCC read and VCC erase currents. 7. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR . 8. If VIN>VCC the input load current increases to 10 A max. 9. ICCS is the average current measured over any 5 ms time interval 5 s after a CE# de-assertion. 10. Refer to section Section 8.2, "Automatic Power Savings" on page 37 for ICCAPS measurement details.
6.2
Note: Table 9:
DC Voltage Characteristics
Specifications are for 130 nm and 90 nm devices unless otherwise stated. DC Voltage Characteristics (Sheet 1 of 2)
VCCQ= 1.8 V
Sym
Parameter
(1)
32/64 Mbit Min Max 0.4 VCCQ 0.1 Min 0
128 Mbit Max 0.4 VCCQ 0.1
Unit
Test Condition
Notes
VIL VIH
Input Low Input High
0 VCCQ - 0.4 --
V V V
-- -- VCC = VCC Min VCCQ = VCCQMin IOL = 100 A VCC = VCC Min VCCQ = VCCQMin IOH = -100 A
3 -- --
VCCQ - 0.4 --
VOL VOH
Output Low
Output High
VCCQ - 0.1
--
VCCQ - 0.1
--
V
--
Datasheet 22
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 9:
DC Voltage Characteristics (Sheet 2 of 2)
V CCQ= 1.8 V
Sym
Parameter
(1)
32/64 Mbit Min Max 0.4 -- -- Min -- 1.0 0.9
128 Mbit Max 0.4 -- --
Unit
Test Condition
Notes
VPPLK VLKO
VILKOQ Note: 1. 2. 3.
VPP Lock-Out VCC Lock
VCCQ Lock
-- 1.0 0.9
V V V --
2 -- --
All currents are RMS unless noted. Typical values at typical VCC , TA = +25 C VPP <= VPPLK inhibits erase and program operations. Don't use VPPL and VPPH outside their valid ranges. VIL can undershoot to -0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
November 2007 Order Number: 313272-06
Datasheet 23
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
7.0
7.1
Figure 5:
AC Characteristics
AC I/O Test Conditions
AC Input/Output Reference Waveform
VCCQ Input 0V
Note: Input timing begins, and output timing ends, at VCCQ /2.
VCCQ/2
Test Points
VCCQ/2
Output
Figure 6:
Transient Equivalent Testing Load Circuit
VCCQ R1
Device Under Test
Out CL R2
Table 10: Test Configuration Component Values
Test Configuration VCCQMin (1.7 V) Standard Test Note: CL includes jig capacitance. CL (pF) 30 R1 (k) 16.7 R2 (k) 16.7
Figure 7:
Clock Input AC Waveform
R201
CLK [C]
VIH VIL R202 R203
7.2
Symbol CIN COUT CCE
TA = +25
Device Capacitance
Parameter Input Capacitance Output Capacitance CE# Input Capacitance Typ 6 8 10 Max 8 12 12 Unit pF pF pF Condition VIN = 0.0 V VOUT = 0.0 V VIN = 0.0 V
C; f = 1 MHz;
Sampled, not 100% tested.
Datasheet 24
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
7.3
AC Read Characteristics, AD-Mux
For timing measurements and maximum allowable slew rate, see Figure 5, "AC Input/ Output Reference Waveform" on page 24. AC specifications assume the data bus voltage is less than or equal to VCCQ when a read operation is initiated.
Note:
Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Table 11: AC Read Characteristics, AD-Mux (Sheet 1 of 2)
# Sym Parameter
(1,2)
60 ns Unit Min Max Notes
Asynchronous Specifications R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH Read Cycle Time Address to Output Delay CE# Low to Output Delay OE# Low to Output Delay RST# High to Output Delay CE# Low to Output in Low-Z OE# Low to Output in Low-Z CE# High to Output in High-Z OE# High to Output in High-Z CE# (OE#) High to Output in Low-Z 60 -- -- -- -- 0 0 -- -- 0 -- 60 60 20 150 -- -- 14 14 -- ns ns ns ns ns ns ns ns ns ns 5 5 5 2 -- 3 2,3 3 2,3 2,3
Latching Specifications R101 R102 R103 R104 R105 R106 R107 Note: 1. 2. 3. 4. 5. tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tVHGL Address Setup to ADV# High CE# Low to ADV# High ADV# Low to Output Delay ADV# Pulse Width Low ADV# Pulse Width High Address Hold from ADV# High ADV# High to OE# Low 7 10 -- 7 7 7 7 -- -- 60 -- -- -- -- ns ns ns ns ns ns ns -- -- 5 -- -- 1 --
Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. OE# may be delayed by up to tELQV- tGLQV after the falling edge of CE# without impact to tELQV. Sampled, not 100% tested. Applies only to subsequent synchronous reads. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus as early as the first clock edge after tAVQV.
November 2007 Order Number: 313272-06
Datasheet 25
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 11: AC Read Characteristics, AD-Mux (Sheet 2 of 2)
# Sym Parameter
(1,2)
60 ns Unit Min Max Notes
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL CLK Frequency CLK Period CLK High or Low Time CLK Fall or Rise Time -- 15 3.5 -- 3 66 MHz ns ns ns -- -- -- --
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 Note: 1. 2. 3. 4. 5. tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV tELTV tEHTZ tEHEL Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Valid Output Hold from CLK Address Hold from CLK CLK to WAIT Valid CE# Low to WAIT Valid CE# High to WAIT High-Z CE# Pulse Width High 3 7 -- -- -- 14 7 7 7 -- -- -- 11 -- -- 11 11 11 -- ns ns ns ns ns ns ns ns ns ns -- -- -- -- -- 1 -- 4 3,4 4
Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. OE# may be delayed by up to tELQV- tGLQV after the falling edge of CE# without impact to tELQV. Sampled, not 100% tested. Applies only to subsequent synchronous reads. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus as early as the first clock edge after tAVQV.
Datasheet 26
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
.
Figure 8:
Single Word Asynchronous Read, AD-Mux
R1
A[MAX:16] [A] A/DQ[15:0] [A/Q]
VIH V IL VIH/OH VIL/OL
Valid Address
Valid Address
High Z
Valid Output
R2 R101 R105 R106
R10
ADV# [V]
VIH V IL R104 R103 R107 R8 R3
CE# [E]
VIH V IL R102
R7
R9
OE# [G]
VIH V IL R4
WE# [W] WAIT [T]
VIH V IL VOH VOL VIH V IL
High Z
Note 1 R5
High Z
RST# [P]
Note:
WAIT signal asserted low [CR.10 = 0]. WAIT signal shown de-asserted.
November 2007 Order Number: 313272-06
Datasheet 27
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 9:
Single Word Synchronous Array Read, AD-Mux
CLK [C] A[MAX:16] [A]
VIH VIL VIH VIL
Valid Address
Note 1
R301
R306
High Z
R304
Valid Output
R305
High Z
A/DQ[15:0] [A/Q]
VIH/OH VIL/OL
Valid Address
R2 R101 R105 R106 R302
R10
ADV# [V]
VIH VIL
R104 R103
R107
R7 R8
CE# [E]
VIH VIL R102
R3
R4
R9
OE# [G]
VIH VIL R303 R308 R309 Note 2
High Z
WAIT [T]
VOH VOL
High Z
WE# [W]
VIH VIL R5
RST# [P]
VIH VIL
Notes: 1. 2.
Section 14.2, "First Access Latency Count (CR[13:11])" on page 67 describes how to insert clock cycles during the initial access. This waveform only illustrates the case in which an x-word burst is initiated to the Main Array and it is terminated by a CE# de-assertion after the first word in the burst. If this access had been done to Status, ID, or Query Space, the activelow WAIT signal would have remained de-asserted (high) as long as CE# is asserted (low).
Datasheet 28
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 10: Synchronous Four-Word Burst Read, AD-Mux
CLK [C] A[MAX:16] [A]
VIH VIL VIH VIL
Valid Address
Note 1
R301
R306
High Z
R304
Valid Output
R305
Valid Output Valid Output Valid Output High Z
A/DQ[15:0] [A/Q]
VIH/OH VIL/OL
Valid Address
R2 R101 R105 R106 R302
R10
ADV# [V]
VIH VIL
R8 R104 R103 R107 R7 R310 R3
CE# [E]
VIH VIL R102
R4
R9
OE# [G]
VIH VIL R303
WE# [W]
VIH VIL R308 R307 R309
High Z
WAIT [T]
VOH VOL
High Z
Note 2
RST# [P]
VIH VIL R5
Notes: 1. 2.
Section 14.2, "First Access Latency Count (CR[13:11])" on page 67 describes how to insert clock cycles during the initial access. WAIT (shown asserted low) can be configured to assert either during or one data cycle before valid data.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 11: WAIT Functionality for EOWL (End of Word Line) Condition, AD-Mux
CLK [C]
VIH VIL R301 R306
High Z
R304
Valid Data14
R305
Valid Data15 Valid Data16 Valid Data17 Valid Data18 Valid Data19
A/DQ[15:0] [A/Q]
VIH VIL
Valid Add14
R2 R101 R105 R106 R302
R10
ADV# [V]
VIH VIL
R8 R104 R107 R103 R7 R310
CE# [E]
VIH VIL R102
R3
R310
R4
R9
OE# [G]
VIH VIL R303
WE# [W]
VIH VIL R309
WAIT [T]
VOH VOL
High Z
R308
RST# [P]
VIH VIL R5
Notes: 1. 2.
Section 14.2, "First Access Latency Count (CR[13:11])" on page 67 describes how to insert clock cycles during the initial access. WAIT (shown asserted low) can be configured to assert either during or one data cycle before valid data.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 12: WAIT Signal in Synchronous Non-Read Array, AD-Mux
CLK [C] A[MAX:16] [A]
V IH VIL V IH VIL
Valid Address
Note 1
R301
R306
High Z
R304
Valid Output
R305
High Z
A/DQ[15:0] [A/Q]
VIH/OH V IL/OL
Valid Address
R2 R101 R105 R106 R302
R10
ADV# [V]
V IH VIL
R104 R103
R107
R7 R8
CE# [E]
V IH VIL R102
R3
R310
R4
R9
OE# [G]
V IH VIL R303
WE# [W]
V IH VIL R307 R309
WAIT [T]
VOH VOL
High Z
Note 2 R308
RST# [P]
V IH VIL R5
Notes: 1. 2.
during the initial access. WAIT signal asserted low [CR.10 = 0]. WAIT signal shown de-asserted.
Section 14.2, "First Access Latency Count (CR[13:11])" on page 67 describes how to insert clock cycles
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 13: Burst Suspend Waveform, AD-Mux
R304 CLK [C] A/DQ [A/DQ] A R101 R105 ADV# [V] CE# [E] R106 Q0
R304 Note 1 Q1 Q1 Q2
R9 OE# [G] R12 WAIT [T] WE# [W]
Note: 1.
R4
During burst suspend, CLK can be held high or low.
7.4
AC Write Characteristics, AD-Mux
Write timing characteristics during an Erase Suspend operation are the same as during Write-Only operations. A Write operation can be terminated with either CE# or WE#.
Note:
Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Table 12: AC Write Characteristics, AD-Mux (Sheet 1 of 2)
# Sym tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) Parameter
(1,2)
60 ns Unit Min Max -- -- -- -- -- ns ns ns ns ns 1 -- 2 -- -- Notes
W1 W2 W3 W4 W5
RST# High Recovery to WE# (CE#) Low CE# (WE#) Setup to WE# (CE#) Low WE# (CE#) Write Pulse Width Low Data Setup to WE# (CE#) High Address Setup to WE# (CE#) High
150 0 40 40 40
Notes: 1. Sampled, not 100% tested. 2. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. 3. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL. 4. tWHQV is tAVQV + 50 ns. Designers should take this into account and may insert a software No-Op instruction to delay the first read after issuing a command. 5. For non-resume commands. 6. VPP should be held at VPP1 or VPP2 until block erase or word program success is determined. 7. Applicable during asynchronous reads following a write. 8. tWHCV and tWHVH refer to the address latching event during a synchronous read. Either tWHCV or tWHVH, whichever comes first, must be met.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 12: AC Write Characteristics, AD-Mux (Sheet 2 of 2)
# Sym tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tVHWH tWHQV tWHAV tWHCV tWHVH Parameter
(1,2)
60 ns Unit Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- -- 3,4,5 1 1, 5 1, 6 1 -- -- 4 7 8 8 Notes
W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W18 W19 W20
CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) High VPP Hold from Valid SRD WP# Hold from Valid SRD WP# Setup to WE# (CE#) High Write Recovery before Read ADV# Setup to WE# High WE# High to Valid Data WE# High to Address Valid WE# High to CLK Valid WE# High to ADV# High
0 0 0 20 200 0 0 200 0 N/A tAVQV +20 0 12 12
Notes: 1. Sampled, not 100% tested. 2. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. 3. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL. 4. tWHQV is tAVQV + 50 ns. Designers should take this into account and may insert a software No-Op instruction to delay the first read after issuing a command. 5. For non-resume commands. 6. VPP should be held at VPP1 or VPP2 until block erase or word program success is determined. 7. Applicable during asynchronous reads following a write. 8. tWHCV and tWHVH refer to the address latching event during a synchronous read. Either tWHCV or tWHVH, whichever comes first, must be met.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 14: Write Operations Waveform, AD-Mux
CLK [C]
VIH VIL VIH VIL
Note 1
Note 2
Valid Address
Note 3
Valid Address
Note 4
Note 5
Valid Address
A[MAX:16] [A] A/DQ[15:0] [A/Q]
VIH/OH VIL/OL
Valid Address
Data In
Valid Address
Data In
Valid Address
Valid Data
W7 R101 R106 W5 R105 W18 VIH VIL R104 W20 W4 W19
ADV# [V]
CE# [E]
VIH VIL W2 W6 W14
Note 6
OE# [G]
VIH VIL VIH VIL W1 W3 W16 W9
WE# [W]
RST# [P] WP# [B]
VIH VIL VIH VIL W10
VPPH
W13
W12
W11
VPP [V]
VPPLK VIL
Notes: 1. 2. 3. 4. 5. 6. 7.
VCC power-up and standby. Write Program or Erase Setup command. Write valid address and data (for program) or Erase Confirm command. Automated program/erase delay. Read status register data (SRD) to determine program/erase operation completion. OE# and CE# must be asserted and WE# de-asserted for read operations. CLK is ignored (but may be kept active/toggling).
7.5
Program and Erase Characteristics
Unless noted otherwise, all Erase and Progrm parameters are measured at TA = +25 C and nominal voltages, and they are sampled, not 100% tested. Some EFP performance degradation may occur if block cycling exceeds 10 attempts.
Note:
Specifications are for 130 nm and 90 nm devices unless otherwise stated.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 13: Erase and Program Times
Operation Symbol Parameter Description Typ Erasing and Suspending Erase Time Suspend Latency Programming W200 Program Time W201 W202 tPROG/W tPROG/PB tPROG/MB Single Word 4-Kword Parameter Block 32-Kword Main Block 12 0.05 0.4 150 0.23 1.8 8 0.03 0.24 130 0.07 0.6 s s s 1 1,2 1,2 W500 W501 W600 W601 tERS/PB tERS/MB tSUSP/P tSUSP/E 4-Kword Parameter Block 32-Kword Main Block Program Suspend Erase Suspend 0.3 0.7 5 5 2.5 4 10 20 0.25 0.4 5 5 2.5 4 10 20 s s s s 1,2 1,2 1 1 VPP1 Max Typ VPP2 Max Unit Notes
Enhanced Factory Programming W400 Program W401 W402 W403 Operation Latency W404 W405 tEFP/W tEFP/PB tEFP/MB tEFP/SETUP tEFP/TRAN tEFP/VERIFY Single Word 4-Kword Parameter Block 32-Kword Main Block EFP Setup Program to Verify Transition Verify N/A N/A N/A -- N/A N/A N/A -- -- N/A N/A N/A 3.1 15 120 -- 2.7 1.7 16 -- -- 5 5.6 130 s ms ms s s s 3 1,2 1,2 -- -- --
Notes: 1. Excludes external system-level overhead. 2. Exact results may vary based on system overhead. 3. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming within a new word-line.
7.6
Note:
Reset Specifications
Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Table 14: Reset Specifications
# P1 P2 P3 Notes: 1. 2. 3. 4. 5. 6. Symbol tPLPH tPLRH tVCCPH Parameter RST# Low to Reset during Read RST# Low to Reset during Block Erase RST# Low to Reset during Program VCC Power Valid to Reset Notes 1, 2, 3, 4 1, 3, 4, 5 1, 3, 4, 5 1,3,4,5,6 Min 100 -- -- 60 Max -- 20 10 -- Unit ns s s s
These specifications are valid for all product versions (packages and speeds). The device may reset if tPLPH< tPLPHMin, but this is not guaranteed. Not applicable if RST# is tied to VCC. Sampled, but not 100% tested. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after when VCC VCC Min. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC VCCMin.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 15: Reset Operations Waveforms
P1
R5
(A) Reset during read mode
RST# [P]
VIH VIL
P2
(B) Reset during program or block erase P1 P2 (C) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P2
Abort Complete
R5
RST# [P]
VIH VIL
P3
(D) VCC Power-up to RST# high
VCC
VCC 0V
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
8.0
Power and Reset Specifications
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO devices have a layered approach to power savings that can significantly reduce overall system power consumption. The APS feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the memory enters its standby mode, where current consumption is even lower. Asserting RST# provides current savings similar to standby mode. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.
8.1
Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 6.1, "DC Current Characteristics" on page 21, for ICC values. When the device is in "active" state, it consumes the most power from the system. Minimizing device active current therefore reduces system power consumption, especially in battery-powered applications.
8.2
Automatic Power Savings
Automatic Power Saving (APS) provides low-power operation during a read's active state. During APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 s after the following events happen: * There is no internal sense activity; * CE# is asserted; * The address lines are quiescent, and at VSSQ or VCCQ. OE# may be asserted during APS.
8.3
Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or program operations, the device continues the operation and consumes corresponding active power until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5 s after a CE# deassertion.
8.4
Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it doesn't matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur when RST# is low.
8.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
will not occur because the flash memory may be providing status information instead of array data. To allow proper CPU/flash initialization at system reset, connect RST# to the system CPU RESET# signal. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits writes to the device. The CUI architecture provides additional protection because alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RST# is brought to VIH, regardless of its control input states. By holding the device in reset (RST# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
8.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after VCC transitions above VLKO (Lockout voltage). After completing program or block erase operations (even after VPP transitions below VPPLK), the Read Array command must reset the CUI to read-array mode if flash memory array access is desired.
8.5
Power Supply Decoupling
When the W18 device is accessed, many internal conditions change. Circuits are enabled to charge pumps and switch voltages. This internal activity produces transient noise. To minimize the effect of this transient noise, device decoupling capacitors are required. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close as possible to package signals.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
9.0
Device Operations
This section provides an overview of device operations. The NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO family includes an on-chip WSM to manage block erase and program algorithms. Its CUI allows minimal processor overhead with RAM-like interface timings.
9.1
Bus Operations
Table 15: Bus Operations
Mode Reset Write Read Output Disable Standby Notes: 1. 2. 3. 4. RST# VIL VIH VIH VIH VIH CE# X VIL VIL VIL VIH OE# X VIH VIL VIH X WE# X VIL VIH VIH X ADV# X VIL VIL X X WAIT High-Z Asserted
Active
DQ[15:0] High-Z DIN DOUT High-Z High-Z
Notes 1,2 3 4 1 1
Asserted High-Z
X = Don't Care (VIL or VIH). RST# must be at VSS 0.2 V to meet the maximum specified power-down current. Refer to the Table 17, "Bus Cycle Definitions" on page 43 for valid DIN during a write operation. WAIT is only valid during synchronous array read operations.
9.1.1
Read
The W18 device has several read configurations: * Asynchronous page mode read. * Synchronous burst mode read -- outputs four, eight, sixteen, or continuous words, from main blocks and parameter blocks. Several read modes are available in each partition: * Read-array mode: read accesses return flash array data from the addressed locations. * Read identifier mode: reads return manufacturer and device identifier data, block lock status, and protection register data. Identifier information can be accessed starting at 4-Mbit partition base addresses; the flash array is not accessible in read identifier mode. * Read query mode: reads return device CFI data. CFI information can be accessed starting at 4-Mbit partition base addresses; the flash array is not accessible in read query mode. * Read status register mode: reads return status register data from the addressed partition. That partition's array data is not accessible. A system processor can check the status register to determine an addressed partition's state or monitor program and erase progress. All partitions support the synchronous burst mode that internally sequences addresses with respect to the input CLK to select and supply data to the outputs. Identifier codes, query data, and status register read operations execute as singlesynchronous or asynchronous read cycles. WAIT is asserted during these reads.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Access to the modes listed above is independent of VPP. An appropriate CUI command places the device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read-array mode. Asserting CE# enables device read operations. The device internally decodes upper address inputs to determine which partition is accessed. Asserting ADV# opens the internal address latches. Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# is deasserted (when the device is configured to use ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST# must be at deasserted during read operations. Note: If only asynchronous reads are to be performed in your system, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground.
9.1.2
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the flash address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains asserted and does not revert to a high-impedance state when OE# is deasserted. This can cause contention with another device attempting to control the system's READY signal during a Burst Suspend. System using the Burst Suspend feature should not connect the device's WAIT signal directly to the system's READY signal. Refer to Figure 13, "Burst Suspend Waveform, AD-Mux" on page 32.
9.1.3
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device power consumption. In standby mode, outputs are placed in a highimpedance state independent of OE#. If deselected during a program or erase algorithm, the device shall consume active power until the program or erase operation completes.
9.1.4
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The device defaults to read-array mode, the status register is set to 80h, and the configuration register defaults to asynchronous page-mode reads. If RST# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Like any automated device, it is important to assert RST# during system reset. When the system comes out of reset, the processor expects to read from the flash memory array. Automated flash memories provide status information when read during program or erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Numonyx Flash memories allow proper CPU initialization following a system reset through the use of the RST# input. In this application, RST# is controlled by the same CPU reset signal, RESET#.
9.1.5
Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control commands are written to the CUI using standard microprocessor write timings. Proper use of the ADV# input is needed for proper latching of the addresses. Write operations are asynchronous; CLK is ignored (but still may be kept active/toggling). The CUI does not occupy an addressable memory location within any partition. The system processor must access it at the correct address range depending on the kind of command executed. Programming or erasing may occur in only one partition at a time. Other partitions must be in one of the read modes or erase suspend mode. Table 16, "Command Codes and Descriptions" on page 41 shows the available commands. Appendix , "Write State Machine States" on page 73 provides information on moving between different operating modes using CUI commands.
9.2
Device Commands
The W18 device on-chip WSM manages erase and program algorithms. This local CPU (WSM) controls the device's in-system read, program, and erase operations. Bus cycles to or from the flash memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the device. WAIT informs the CPU of valid data during burst reads. Table 15, "Bus Operations" on page 39 summarizes bus operations. Device operations are selected by writing specific commands into the device's CUI. Table 16, "Command Codes and Descriptions" on page 41 lists all possible command codes and descriptions. Table 17, "Bus Cycle Definitions" on page 43 lists command definitions. Because commands are partition-specific, it is important to issue write commands within the target address range.
Table 16: Command Codes and Descriptions (Sheet 1 of 2)
Operation Code FFh 70h Device Command Read Array Read Status Register Read Identifier Description Places selected partition in read-array mode. Places selected partition in status register read mode. The partition enters this mode after a Program or Erase command is issued to it. Puts the selected partition in read identifier mode. Device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, or protection register data on D[15:0]. Puts the addressed partition in read query mode. Device reads from the partition addresses output CFI information on D[7:0]. The WSM can set the status register's block lock (SR[1]), VPP (SR[3]), program (SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can only be cleared by a device reset or through the Clear Status Register command.
Read
90h
98h
Read Query Clear Status Register
50h
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 16: Command Codes and Descriptions (Sheet 2 of 2)
Operation Code Device Command Description This preferred program command's first cycle prepares the CUI for a program operation. The second cycle latches address and data, and executes the WSM program algorithm at this location. Status register updates occur when CE# or OE# is toggled. A Read Array command is required to read array data after programming. Equivalent to a Program Setup command (40h). This program command activates EFP mode. The first write cycle sets up the command. If the second cycle is an EFP Confirm command (D0h), subsequent writes provide program data. All other commands are ignored after EFP mode begins. If the first command was EFP Setup (30h), the CUI latches the address and data, and prepares the device for EFP mode. This command prepares the CUI for Block Erase. The device erases the block addressed by the Erase Confirm command. If the next command is not Erase Confirm, the CUI sets status register bits SR[5:4] to indicate command sequence error and places the partition in the read status register mode. If the first command was Erase Setup (20h), the CUI latches address and data, and erases the block indicated by the erase confirm cycle address. During program or erase, the partition responds only to Read Status Register, Program Suspend, and Erase Suspend commands. CE# or OE# toggle updates status register data. This command, issued at any device address, suspends the currently executing program or erase operation. Status register data indicates the operation was successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend) and SR[7] are set. The WSM remains in the suspended state regardless of control signal states (except RST#). This command, issued at any device address, resumes the suspended program or erase operation. This command prepares the CUI lock configuration. If the next command is not Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate command sequence error. If the previous command was Lock Setup (60h), the CUI locks the addressed block. If the previous command was Lock Setup (60h), the CUI latches the address and unlocks the addressed block. If previously locked-down, the operation has no effect. If the previous command was Lock Setup (60h), the CUI latches the address and locks-down the addressed block. This command prepares the CUI for a protection register program operation. The second cycle latches address and data, and starts the WSM's protection register program or lock algorithm. Toggling CE# or OE# updates the flash status register data. To read array data after programming, issue a Read Array command. This command prepares the CUI for device configuration. If Set Configuration Register is not the next command, the CUI sets SR[5:4] to indicate command sequence error. If the previous command was Configuration Setup (60h), the CUI latches the address and writes the data from A[15:0] into the configuration register. Subsequent read operations access array data.
40h
Word Program Setup
Program
10h
Alternate Setup
30h
EFP Setup
D0h
EFP Confirm
20h Erase D0h
Erase Setup
Erase Confirm
B0h Suspend D0h
Program Suspend or Erase Suspend
Suspend Resume
60h
Lock Setup
01h Block Locking D0h
Lock Block
Unlock Block
2Fh
Lock-Down Protection Program Setup Configuration Setup Set Configuration Register
Protection
C0h
60h Configuration 03h Note:
Do not use unassigned commands. Numonyx reserves the right to redefine these codes for future functions.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 17: Bus Cycle Definitions
Operation Command Bus Cycles 1 2 2 2 1 2 2 >2 1 1 2 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 PnA PnA PnA PnA XX BA WA WA XX XX BA BA BA PA Data2,3 FFh 90h 98h 70h 50h 20h 40h/10h 30h B0h D0h 60h 60h 60h C0h Second Bus Cycle Oper Read Read Read Read -- Write Write Write -- -- Write Write Write Write Addr1 Read Address PBA+IA PBA+QA PnA -- BA WA WA -- -- BA BA BA PA Data2,3 Array Data IC QD SRD -- D0h WD D0h -- -- 01h D0h 2Fh PD
Read Array/Reset Read Identifier Read Read Query Read Status Register Clear Status Register Block Erase Program and Erase Word Program EFP Program/Erase Suspend Program/Erase Resume Lock Block Lock Unlock Block Lock-Down Block Protection Program Protection Lock Protection Program
2
Write
LPA
C0h
Write
LPA
FFFDh
Configuration
Set Configuration Register
2
Write
CD
60h
Write
CD
03h
Notes: 1. First-cycle command addresses should be the same as the operation's target address. Examples: the first-cycle address for the Read Identifier command should be the same as the Identification code address (IA); the first-cycle address for the Word Program command should be the same as the word address (WA) to be programmed; the first-cycle address for the Erase/Program Suspend command should be the same as the address within the block to be suspended; etc. XX = Any valid address within the device. IA = Identification code address. BA = Block Address. Any address within a specific block. LPA = Lock Protection Address is obtained from the CFI (through the Read Query command). The W18 family's LPA is at 0080h. PA = User programmable 4-word protection address. PnA = Any address within a specific partition. PBA = Partition Base Address. The very first address of a particular partition. QA = Query code address. WA = Word address of memory location to be written. 2. SRD = Status register data. WD = Data to be written at location WA. IC = Identifier code data. PD = User programmable 4-word protection data. QD = Query code data on DQ[7:0]. CD = Configuration register code data presented on device addresses A/DQ[15:0]. A[MAX:16] address bits can select any partition. See Table 25, "Configuration Register Definitions" on page 66 for configuration register bits descriptions. 3. Commands other than those shown above are reserved by Numonyx for future device implementations and should not be used.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
9.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed partition into read-status mode, so if the same partition is read before the second "confirm" write cycle is issued, status register data will be returned. Reads from other partitions, however, can return actual array data assuming the addressed partition is already in read-array mode. Figure 16 on page 44 and Figure 17 on page 44 illustrate these two conditions.
Figure 16: Normal Write and Read Cycles
Address [A] WE# [W] OE# [G] Data [Q]
Partition A
Partition A
Partition A
20h
Block Erase Setup
D0h
Block Erase Conf irm
FFh
Read Array
Figure 17: Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A] WE# [W] OE# [G] Data [Q]
Partition B
Partition A
Partition B
Partition A
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Conf irm
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a command sequence error to appear in the status register. Figure 18 illustrates a command sequence error. Figure 18: Improper Command Sequencing
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition X
Partitio n Y
Partition X
Partiti on X
20h
FFh
D0h
SR Data
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November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
10.0
10.1
Read Operations
Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions from VIL to VIH), all partitions default to asynchronous readarray mode. To read array data from the flash device, first write the Read Array command (FFh) to the CUI and specify the desired word address. Then read from that address. If a partition is already in read-array mode, the Read Array command need not be reissued to read from that partition. If the Read Array command is written to a partition that is erasing or programming, the device presents invalid data on the bus until the program or erase operation completes. After the program or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program Suspend command suspends the WSM, a subsequent Read Array command places the addressed partition in read-array mode. The Read Array command functions independently of VPP.
10.2
Read Device ID
The read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register data. The identifier information is contained within a separate memory space on the device and can be accessed along the 4-Mbit partition address range supplied by the Read Identifier command (90h) address. Reads from addresses in Table 18 retrieve ID information. Issuing a Read Identifier command to a partition that is programming or erasing places that partition's outputs in read ID mode while the partition continues to program or erase in the background.
Table 18: Device Identification Codes (Sheet 1 of 2)
Address(1) Item Base Manufacturer ID Partition Offset 00h 0089h 8872h Device ID (Top Parameter) Partition 01h 8874h 8876h 8873h Device ID (Bottom Parameter) Partition 01h 8875h 8877h Block Lock Status (2) Block 02h A/DQ[0] = 0 A/DQ[0] = 1 A/DQ[1] = 0 A/DQ[1] = 1 Numonyx 32-Mbit TPD 64-Mbit TPD 128-Mbit TPD 32-Mbit BPD 64-Mbit BPD 128-Mbit BPD Block is unlocked Block is locked Block is not locked-down Block is locked down Data Description
Block Lock-Down Status(2)
Block
02h
Notes: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 39 in a TPD, set the address to the BBA (138000h) plus the offset (02h), i.e. 138002h. Then examine bit 0 of the data to determine if the block is locked. 2. See Section 13.1.4, "Block Lock Status" on page 61 for valid lock status.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 18: Device Identification Codes (Sheet 2 of 2)
Address(1) Item Base Configuration Register Protection Register Lock Status Protection Register Partition Partition Partition Offset 05h 80h 81h - 88h Register Data Lock Data Register Data -- -- Multiple reads required to read the entire 128-bit Protection Register. Data Description
Notes: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 39 in a TPD, set the address to the BBA (138000h) plus the offset (02h), i.e. 138002h. Then examine bit 0 of the data to determine if the block is locked. 2. See Section 13.1.4, "Block Lock Status" on page 61 for valid lock status.
10.3
Read Query (CFI)
This device contains a separate CFI query database that acts as an "on-chip datasheet." The CFI information within this device can be accessed by issuing the Read Query command and supplying a specific address. The address is constructed from the base address of a partition plus a particular offset corresponding to the desired CFI field. Section 16.0, "Common Flash Interface" on page 76 shows accessible CFI fields and their address offsets. Issuing the Read Query command to a partition that is programming or erasing puts that partition in read query mode while the partition continues to program or erase in the background.
10.4
Read Status Register
The device's status register displays program and erase operation status. A partition's status can be read after writing the Read Status Register command to any location within the partition's address range. Read-status mode is the default read mode following a Program, Erase, or Lock Block command sequence. Subsequent single reads from that partition will return its status until another valid command is written. The read-status mode supports single synchronous and single asynchronous reads only; it doesn't support burst reads. The first falling edge of OE# or CE# latches and updates status register data. The operation doesn't affect other partitions' modes. Because the status register is 8 bits wide, only DQ [7:0] contains valid status register data; DQ [15:8] contains zeros. See Table 19, "Status Register Definitions" on page 46 and Table 20, "Status Register Descriptions" on page 47. Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides program and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit, SR[0], provides program and erase status of the addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, VPP, and block-lock states. Table 21, "Status Register Device WSM and Partition Write Status Description" on page 47 presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Table 19: Status Register Definitions
DWS 7 ESS 6 ES 5 PS 4 VPPS 3 PSS 2 DPS 1 PWS 0
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 20: Status Register Descriptions
Bit 7 Name DWS Device WSM Status ESS Erase Suspend Status ES Erase Status PS Program Status VPPS VPP Status PSS Program Suspend Status DPS Device Protect Status PWS Partition Write Status State 0 = Device WSM is Busy 1 = Device WSM is Ready 0 = Erase in progress/completed 1 = Erase suspended 0 = Erase successful 1 = Erase error 0 = Program successful 1 = Program error 0 = VPP OK 1 = VPP low detect, operation aborted 0 = Program in progress/completed 1 = Program suspended 0 = Unlocked 1 = Aborted erase/program attempt on locked block 0 = This partition is busy, but only if SR[7]=0 1 = Another partition is busy, but only if SR[7]=0 Description SR[7] indicates erase or program completion in the device. SR[6:1] are invalid while SR[7] = 0. After issuing an Erase Suspend command, the WSM halts and sets SR[7] and SR[6]. SR[6] remains set until the device receives an Erase Resume command. SR[5] is set if an attempted erase failed. A Command Sequence Error is indicated when SR[7,5:4] are set. SR[4] is set if the WSM failed to program a word. The WSM indicates the VPP level after program or erase completes. SR[3] does not provide continuous VPP feedback and isn't guaranteed when VPP VPP1/2. After receiving a Program Suspend command, the WSM halts execution and sets SR[7] and SR[2]. They remain set until a Resume command is received. If an erase or program operation is attempted to a locked block (if WP# = VIL), the WSM sets SR[1] and aborts the operation. Addressed partition is erasing or programming. In EFP mode, SR[0] indicates that a data-stream word has finished programming or verifying depending on the particular EFP phase.
6
5 4
3
2
1
0
Table 21: Status Register Device WSM and Partition Write Status Description
DWS: SR[7] 0 0 1 1 PWS: SR[0] 0 1 0 1 Description The addressed partition is performing a program/erase operation. EFP: device has finished programming or verifying data, or is ready for data. A partition other than the one currently addressed is performing a program/erase operation. EFP: the device is either programming or verifying data. No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2]) indicate whether other partitions are suspended. EFP: the device has exited EFP mode. Won't occur in standard program or erase modes. EFP: this combination does not occur.
10.5
Clear Status Register
The Clear Status Register command clears the status register and leaves all partition output states unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they can only be cleared by the Clear Status Register command. By allowing system software to reset these bits, several operations, such as cumulatively programming several addresses or erasing multiple blocks in sequence, can be performed before reading the status register to determine error occurrence. If an error is detected, the Status Register must be cleared before beginning another command or sequence. Device reset (RST# = VIL) also clears the status register. This command functions independently of VPP.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
11.0
11.1
Program Operations
Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed events to program a word at the desired address and verify that the bits are sufficiently programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not change the memory cell contents. Programming can occur in only one partition at a time. All other partitions must be in either a read mode or erase suspend mode. Only one partition can be in erase suspend mode at a time. The status register can be examined for program progress by reading any address within the partition that is busy programming. However, while most status register bits are partition-specific, the Device WSM Status bit, SR[7], is device-specific; that is, if the status register is read from any other partition, SR[7] indicates program status of the entire device. This permits the system CPU to monitor program progress while reading the status of other partitions. CE# or OE# toggle (during polling) updates the status register. Several commands can be issued to a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and Read Query. The Read Array command can also be issued, but the read data is indeterminate. After programming completes, three status register bits can signify various possible error conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM couldn't execute the Word Program command because VPP was outside acceptable limits. If SR[1] is set, the program was aborted because the WSM attempted to program a locked block. After the status register data is examined, clear it with the Clear Status Register command before a new command is issued. The partition remains in status register mode until another command is written to that partition. Any command can be issued after the status register indicates program completion. If CE# is deasserted while the device is programming, the devices will not enter standby mode until the program operation completes.
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November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 19: Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Bus Command Operation Write Program Setup Data Comments Data = 40h Addr = Location to program (WA) Data = Data to program (WD) Addr = Location to program (WA) Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy
Write 40h, Word Address Write Data Word Address
Write
Read Read Status Register
No
Suspend Program Loop
0
Standby
SR[7] =
1
Suspend Program
Yes
Repeat for subsequent programming operations. Full status register check can be done after each program or after a sequence of program operations.
Full Program Status Check (if desired) Program Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Standby SR[3] =
0 1 1
Comments Check SR[3] 1 = VPP error Check SR[4] 1 = Data program error Check SR[1] 1 = Attempted program to locked block Program aborted
VPP Range Error Standby Program Error
SR[4] =
0
Standby
SR[1] =
0
1
Device Protect Error
SR[3] MUST be cleared before the WSM will allow further program attempts Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery.
Program Successful
11.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through VCC. If VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from VPP. This eliminates the need for an external switching transistor to control the VPP voltage. Figure 28, "Examples of VPP Power Supply Configurations" on page 65 shows examples of flash power supply usage in various configurations.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
The 12 V VPP mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use.12 V may be applied to VPP during program and erase operations as specified in Section 5.2, "Operating Conditions" on page 20. VPP may be connected to 12 V for a total of tPPH hours maximum. Stressing the device beyond these limits may cause permanent damage.
11.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm eliminates the traditional overhead delays of the conventional word program mode in both the host programming system and the flash device. Changes to the conventional word programming flowchart and internal WSM routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was attained. The host programmer writes data to the device and checks the Status Register to determine when the data has completed programming. This modification essentially cuts write bus cycles in half. Following each internal program pulse, the WSM increments the device's address to the next physical location. Now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. In combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. EFP further speeds up programming by performing internal code verification. With this, PROM programmers can rely on the device to verify that it has been programmed properly. From the device side, EFP streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. EFP consists of four phases: setup, program, verify and exit. Refer to Figure 20, "Enhanced Factory Program Flowchart" on page 52 for a detailed graphical representation of how to implement EFP.
11.3.1
EFP Requirements and Considerations
Table 22: EFP Requirements and Considerations
Ambient temperature: TA = 25 C 5 C EFP Requirements VCC within specified operating range VPP within specified VPP2 range Target block unlocked Block cycling below 100 erase cycles EFP Considerations RWW not supported2
1
EFP programs one block at a time EFP cannot be suspended
Notes: 1. Recommended for optimum performance. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 2. Code or data cannot be read from another partition during EFP.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
11.3.2
Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1] are set and EFP operation terminates.
Note:
After the EFP Setup and Confirm command sequence, reads from the device automatically output status register data. Do not issue the Read Status Register command; it will be interpreted as data to program at WA0.
11.3.3
Program
After setup completion, the host programming system must check SR[0] to determine "data-stream ready" status (SR[0]=0). Each subsequent write after this is a programdata write to the flash array. Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the program pulse. The host programmer must poll the device's status register for the "program done" state after each data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location have received their single WSM program pulse, and that the device is now ready for the next word. Although the host may check full status for errors at any time, it is only necessary on a block basis, after EFP exit. Addresses must remain within the target block. Supplying an address outside the target block immediately terminates the program phase; the WSM then enters the EFP verify phase. The address can either hold constant or it can increment. The device compares the incoming address to that stored from the setup phase (WA0); if they match, the WSM programs the new data word at the next sequential memory location. If they differ, the WSM jumps to the new address location. The program phase concludes when the host programming system writes to a different block address, and data supplied must be FFFFh. Upon program phase completion, the device enters the EFP verify phase.
11.3.4
Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that do not completely program on their first attempt, EFP internal verification identifies them and applies additional pulses as required. The verify phase is identical in flow to the program phase, except that instead of programming incoming data, the WSM compares the verify-stream data to that which was previously programmed into the block. If the data compares correctly, the host programmer proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s). The host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. It then reissues each data word in the same order as during the program phase. Like programming, the host may write each subsequent data word to WA0 or it may increment up through the block addresses. The verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the EFP exit phase.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
11.3.5
Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. After EFP exit, any valid CUI command can be issued.
Figure 20: Enhanced Factory Program Flowchart
EFP Setup
Start
EFP Program
Read Status Register
EFP Verify
Read Status Register
EFP Exit
Read Status Register
VPP = 12V Unlock Block
SR[0]=1=N
Data Stream Ready? SR[0] =0=Y Write Data Address = WA0
SR[0]=1=N Verify Stream Ready? SR[0] =0=Y Write Data Address = WA0
SR[7]=0=N
EFP Exited? SR[7]=1=Y Full Status Check Procedure
Write 30h Address = WA0
Write D0h Address = WA0 S R [0 ]= 1 = N
EFP setup time
S R [7 ]= 0 = Y
Read Status Register
Program Done? SR[0]=0=Y
S R [0 ]= 1 = N
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR[0]=0=Y
EFP Setup Done? SR[7]=1=N Check VPP & Lock errors (SR[3,1])
N
Last Data? Y Write FFFFh Address BBA
N
Last Data? Y Write FFFFh Address BBA
Exit
EFP Setup
Bus State Write Write Write Standby Read Standby EFP Setup Done? Unlock Block EFP Setup Comments VPP = 12V Unlock block Data = 30h Address = WA0 Bus State Read
EFP Program
Comments Status Register Bus State Read
EFP Verify
Comments Status Register
Data Check SR[0] Standby Stream 0 = Ready for data Ready? 1 = Not ready for data Write (note 1) Read Data = Data to program Address = WA0 Status Register
Verify Check SR[0] Standby Stream 0 = Ready for verify Ready? 1 = Not ready for verify Write (note 2) Read Standby (note 3) Standby Verify Done? Last Data? Exit Verify Phase Data = Word to verify Address = WA0 Status Register Check SR[0] 0 = Verify done 1 = Verify not done Device automatically increments address. Data = FFFFh Address not within same BBA
EFP Data = D0h Confirm Address = WA0 EFP setup time Status Register Check SR[7] 0 = EFP ready 1 = EFP not ready
Check SR[0] Program 0 = Program done Standby Done? 1 = Program not done Standby Last Data? Device automatically increments address.
If SR[7] = 1: Error Check SR[3,1] Standby Condition SR[3] = 1 = VPP error Check SR[1] = 1 = locked block
Write
Exit Data = FFFFh Program Address not within same Phase BBA
Write
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base Read Status Register Address) must remain constant throughout the program phase data stream; WA can be held Check SR[7] constant at the first address location, or it can be written to sequence up through the addresses EFP 0 = Exit not finished Standby within the block. Writing to a BBA not equal to that of the block currently being written to Exited? 1 = Exit completed terminates the EFP program phase, and instructs the device to enter the EFP verify phase. 2. For proper verification to occur the verify data stream must be presented to the device in the , Repeat for subsequent operations. same sequence as that of the program phase data stream. Writing to a BBA not equal to WA After EFP exit, a Full Status Check can terminates the EFP verify phase, and instructs the device to exit EFP . determine if any program error occurred. 3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive additional program-pulse attempts during the EFP verify phase. The device will report any program failure by setting SR[4]=1; this check can be performed during the full status check afterSee the Full Status Check procedure in the Word Program flowchart. EFP has been exited for that block, and will indicate any error within the entire data stream.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
12.0
12.1
Program and Erase Operations
Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase operation. The command can be issued at any device address. The partition corresponding to the command's address remains in its previous state. A suspend command allows data to be accessed from memory locations other than the one being programmed or the block being erased. A program operation can be suspended only to perform a read operation. An erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. A program command nested within a suspended erase can subsequently be suspended to read yet another location. Once a program or erase process starts, the Suspend command requests that the WSM suspend the program or erase sequence at predetermined points in the algorithm. The partition that is actually suspended continues to output status register data after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6] and/or SR[2] are set. To read data from blocks within the partition (other than an erase-suspended block), you can write a Read Array command. Block erase cannot resume until the program operations initiated during erase suspend are complete. Read Array, Read Status Register, Read Identifier (ID), Read Query, and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block are valid commands during erase suspend. To read data from a block in a partition that is not programming or erasing, the operation does not need to be suspended. If the other partition is already in read array, ID, or Query mode, issuing a valid address returns corresponding data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP must remain at its program level and WP# must remain unchanged while in suspend mode. A resume command instructs the WSM to continue programming or erasing and clears status register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition. When read at the partition that is programming or erasing, the device outputs data corresponding to the partition's last mode. If status register error bits are set, the status register can be cleared before issuing the next instruction. RST# must remain at VIH. See Figure 21, "Program Suspend / Resume Flowchart" on page 54, and Figure 22, "Erase Suspend / Resume Flowchart" on page 55. If a suspended partition was placed in read array, read status register, read identifier (ID), or read query mode during the suspend, the device remains in that mode and outputs data corresponding to that mode after the program or erase operation is resumed. After resuming a suspended operation, issue the read command appropriate to the read operation. To read status after resuming a suspended operation, issue a Read Status Register command (70h) to return the suspended partition to status mode.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 21: Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Start
Program Suspend
Bus Command Operation Write
Comments
Write B0h Any Address
Read Status
Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status Data = 70h Addr = Same partition Status register data Toggle CE# or OE# to update Status register Addr = Suspended block (BA) Check SR.7 1 = WSM ready 0 = WSM busy Check SR.2 1 = Program suspended 0 = Program completed Read Array Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Program Data = D0h Resume Addr = Suspended block (BA)
Write
Write 70h Same Partition Read Status Register Read
SR.7 =
1
0
Standby
SR.2 =
Read 1 Array
0
Program Completed
Standby
Write
Write FFh Susp Partition Read Read Array Data
Write
No
Done Reading
Yes Program Resume
If the suspended partition was placed in Read Array mode: Write
Read Array
Read Status
Return partition to Status mode: Data = 70h Addr = Same partition
Write D0h Any Address Program Resumed
Read Status
Write FFh Pgm'd Partition Read Array Data
Write 70h Same Partition
PGM_SUS.WMF
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 22: Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Erase Suspend
Bus Command Operation Write Erase Suspend Read Status
Comments Data = B0h Addr = Any address Data = 70h Addr = Same partition Status register data. Toggle CE# or OE# to update Status register Addr = Same partition Check SR.7 1 = WSM ready 0 = WSM busy Check SR.6 1 = Erase suspended 0 = Erase completed
Write B0h Any Address
Read Status
Write
Write 70h Same Partition Read Read Status Register Standby SR.7 =
1 0 0
Standby Erase Completed Write Read or Write Write Program Resume
SR.6 =
1
Read Array Data = FFh or 40h or Program Addr = Block to program or read Read array or program data from/to block other than the one being erased Data = D0h Addr = Any address
Read
Read or Program?
No
Program
Read Array Data
Program Loop
Done?
Erase Yes Resume Read Array
If the suspended partition was placed in Read Array mode or a Program Loop: Write Read Status Return partition to Status mode: Data = 70h Addr = Same partition
Write D0h Any Address
Write FFh Erased Partition Read Array Data
Erase Resumed
Read Status
Write 70h Same Partition
ERAS_SUS.WMF
12.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm (D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode at a time; other partitions must be in a read mode. The Erase Confirm command internally latches the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared while the erase executes. After writing the Erase Confirm command, the selected partition is placed in read status register mode and reads performed to that partition return the current status data. The address given during the Erase Confirm command does not need to be the same address used in the Erase Setup command. So, if the Erase Confirm command is given to partition B, then the selected block in partition B will be erased even if the Erase Setup command was to partition A.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase Setup command must be immediately followed by the Erase Confirm command in order to execute properly. If a different command is issued between the setup and confirm commands, the partition is placed in read-status mode, the status register signals a command sequence error, and all subsequent erase commands to that partition are ignored until the status register is cleared. The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit (SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register command before attempting the next operation. The partition remains in read-status mode until another command is written to its CUI. Any CUI instruction can follow after erasing completes. The CUI can be set to read-array mode to prevent inadvertent status register reads.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 23: Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Bus Command Comments Operation Block Data = 20h Erase Write Addr = Block to be erased (BA) Setup Write Write D0h and Block Address Read Read Status Register
No
Write 20h Block Address
Erase Confirm
Data = D0h Addr = Block to be erased (BA) Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy
Suspend Erase Loop
0
Standby
SR[7] =
1
Suspend Erase
Yes
Repeat for subsequent block erasures. Full status register check can be done after each block erase or after a sequence of block erasures.
Full Erase Status Check (if desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register
1
Bus Command Operation VPP Range Error Command Sequence Error Block Erase Error Erase of Locked Block Aborted Standby Standby Standby Standby Check SR[3] 1 = VPP error
Comments
SR[3] =
0
Check SR[5:4] Both 1 = Command sequence error Check SR[5] 1 = Block erase error
SR[5:4] =
0
1
SR[5] =
0
1
SR[1] =
0
1
Check SR[1] 1 = Attempted erase of locked block Erase aborted SR[3,1] must be cleared before the WSM will allow further erase attempts. Only the Clear Status Register command clears SR[5:3,1]. If an error is detected, clear the Status register before attempting an erase retry or other error recovery.
Block Erase Successful
12.3
Read-While-Write and Read-While-Erase
The NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO supports flexible multi-partition dual-operation architecture. By dividing the flash memory into many separate partitions, the device can read from one partition while programing or erasing in another partition; hence the terms, RWW and RWE. Both of these features greatly enhance data storage performance.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
The product does not support simultaneous program and erase operations. Attempting to perform operations such as these results in a command sequence error. Only one partition can be programming or erasing while another partition is reading. However, one partition may be in erase suspend mode while a second partition is performing a program operation, and yet another partition is executing a read command. Table 16, "Command Codes and Descriptions" on page 41 describes the command codes available for all functions.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
13.0
Security Modes
The NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO offers both hardware and software security features to protect the flash data. The software security feature is used by executing the Lock Block command. The hardware security feature is used by executing the Lock-Down Block command and by asserting the WP# signal. Refer to Figure 24, "Block Locking State Diagram" on page 60 for a state diagram of the flash security features. Also see Figure 25, "Locking Operations Flowchart" on page 62.
13.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. This locking scheme offers two levels of protection. The first allows software-only control of block locking (useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed (protects infrequently changed code blocks). The following sections discuss the locking system operation. The term "state [abc]" specifies locking states; for example, "state [001]," where a = WP# value, b = block lock-down status bit D1, and c = Block Lock status register bit D0. Figure 24, "Block Locking State Diagram" on page 60 defines possible locking states. The following summarizes the locking functionality. * All blocks power-up in a locked state. * Unlock commands can unlock these blocks, and lock commands can lock them again. * The Lock-Down command locks a block and prevents it from being unlocked when WP# is asserted. -- Locked-down blocks can be unlocked or locked with commands as long as WP# is deasserted -- The lock-down status bit is cleared only when the device is reset or powereddown. Block lock registers are not affected by the VPP level. They may be modified and read even if VPP VPPLK. Each block's locking status can be set to locked, unlocked, and lock-down, as described in the following sections. See Figure 25, "Locking Operations Flowchart" on page 62.
November 2007 Order Number: 313272-06
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 24: Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
WP# Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control
Notes:
1. [a,b,c] represents [WP#, D1, D0]. X = Don't Care. 2. D1 indicates block Lock-down status. D1 = `0', Lock-down has not been issued to this block. D1 = `1', Lock-down has been issued to this block. 3. D0 indicates block lock status. D0 = `0', block is unlocked. D0 = `1', block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states.
13.1.1
Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully protected from alteration. Attempted program or erase operations to a locked block will return an error in SR[1]. Unlocked blocks can be locked by using the Lock Block command sequence. Similarly, a locked block's status can be changed to unlocked or lock-down using the appropriate software commands.
13.1.2
Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered-down. An unlocked block's status can be changed to the locked or locked-down state using the appropriate software commands. A locked block can be unlocked by writing the Unlock Block command sequence if the block is not locked-down.
13.1.3
Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection beyond that of a regular locked block. A block that is locked-down cannot have it's state changed by software if WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-Down command should be issued prior asserting WP# will put that block back to the locked-down state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by the Unlock Block command.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
13.1.4
Block Lock Status
Every block's lock status can be read in read identifier mode. To enter this mode, issue the Read Identifier command to the device. Subsequent reads at Block Base Address + 02h will output that block's lock status. For example, to read the block lock status of block 10, the address sent to the device should be 50002h (for a top-parameter device). The lowest two data bits of the read data, D1 and D0, represent the lock status. D0 indicates the block lock status. It is set by the Lock Block command and cleared by the Block Unlock command. It is also set when entering the lock-down state. D1 indicates lock-down status and is set by the Lock-Down command. The lock-down status bit cannot be cleared by software-only by device reset or power-down. See Table 23.
Table 23: Write Protection Truth Table
VPP X VIL X X WP# X X VIL VIH RST# VIL VIH VIH VIH Device inaccessible Word program and block erase prohibited All lock-down blocks locked All lock-down blocks can be unlocked Write Protection
13.1.5
Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using the standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful when another block requires immediate updating. To change block locking during an erase operation, first write the Erase Suspend command. After checking SR[6] to determine the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. After completing lock, unlock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits change immediately. When the erase operation is resumed, it will complete normally. Locking operations cannot occur during program suspend. Appendix , "Write State Machine States" on page 73 shows valid commands during erase suspend.
13.1.6
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Because locking changes require 2-cycle command sequences, for example, 60h followed by 01h to lock a block, following the Configuration Setup command (60h) with an invalid command produces a command sequence error (SR[5:4]=11b). If a Lock Block command error occurs during erase suspend, the device sets SR[4] and SR[5] to 1 even after the erase is resumed. When erase is complete, possible errors during the erase cannot be detected from the status register because of the previous locking command error. A similar situation occurs if a program operation error is nested within an erase suspend.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
13.1.7
WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# only affects blocks that once had the Lock-Down command written to them. After the lockdown status bit is set for a block, asserting WP# forces that block into the lock-down state [011] and prevents it from being unlocked. After WP# is deasserted, the block's state reverts to locked [111] and software commands can then unlock the block (for erase or program operations) and subsequently re-lock it. Only device reset or powerdown can clear the lock-down status bit and render WP# ineffective.
Figure 25: Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Bus Command Operation Write 60h Block Address Write 01,D0,2Fh Block Address Write 90h BBA + 02h Optional Read Block Lock Status Write Lock Setup Comments Data = 60h Addr = Block to lock/unlock/lock-down (BA)
Write
Lock, Data = 01h (Lock block) Unlock, or D0h (Unlock block) Lockdown 2Fh (Lockdown block) Confirm Addr = Block to lock/unlock/lock-down (BA) Read ID Plane Data = 90h Addr = BBA + 02h
Write (Optional)
Read Block Lock Block Lock status data (Optional) Status Addr = BBA + 02h
No
Locking Change?
Yes
Standby (Optional) Read Array
Confirm locking change on DQ[1:0]. (See Block Locking State Transitions Table for valid combinations.) Data = FFh Addr = Any address in same partition
Write FFh Partition Address Lock Change Complete
Write
13.2
Protection Register
The W18 device includes a 128-bit protection register. This protection register is used to increase system security and for identification purposes. The protection register value can match the flash component to the system's CPU or ASIC to prevent device substitution. The lower 64 bits within the protection register are programmed by Numonyx with a unique number in each flash device. The upper 64 OTP bits within the protection register are left for the customer to program. Once programmed, the customer segment can be locked to prevent further programming.
Note:
The individual bits of the user segment of the protection register are OTP, not the register in total. The user may program each OTP bit individually, one at a time, if desired. After the protection register is locked, however, the entire user segment is locked and no more user bits can be programmed.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
The protection register shares some of the same internal flash resources as the parameter partition. Therefore, RWW is only allowed between the protection register and main partitions. Table 24 describes the operations allowed in the protection register, parameter partition, and main partition during RWW and RWE. Table 24: Simultaneous Operations Allowed with the Protection Register
Protection Register Parameter Partition Array Data See Description Main Partitions Description While programming or erasing in a main partition, the protection register can be read from any other partition. Reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers from parameter partition addresses is not allowed. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers in a partition that is different from the one being programmed or erased, and also different from the parameter partition, is allowed. While programming the protection register, reads are only allowed in the other main partitions. Access to the parameter partition is not allowed. This is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. While programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. Reads in other main partitions are supported.
Read
Write/Erase
See Description
Read
Write/Erase
Read
Read
Write/Erase
Write
No Access Allowed
Read
No Access Allowed
Write/Erase
Read
13.2.1
Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time from addresses shown in Table 18, "Device Identification Codes" on page 45. The protection register is read from the Read Identifier command and can be read in any partition.Writing the Read Array command returns the device to read-array mode.
13.2.2
Programing the Protection Register
The Protection Program command should be issued only at the parameter (top or bottom) partition followed by the data to be programmed at the specified location. It programs the upper 64 bits of the protection register 16 bits at a time. Table 18, "Device Identification Codes" on page 45 shows allowable addresses. See also Figure 26, "Protection Register Programming Flowchart" on page 64. Issuing a Protection Program command outside the register's address space results in a status register error (SR[4]=1).
13.2.3
Locking the Protection Register
PR-LK.0 is programmed to 0 by Numonyx to protect the unique device number. PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (See Figure 27, "Protection Register Locking"). This bit is set using the Protection Program command to program "FFFDh" into PR-LK. After PR-LK register bits are programmed (locked), the protection register's stored values can't be changed. Protection Program commands written to a locked section result in a status register error (SR[4]=1, SR[5]=1).
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 26: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start Bus Command Comments Operation Protection Data = C0h Program Write Addr = Protection address Setup Write Write Protect. Register Address / Data Read Status Register Protection Data = Data to program Program Addr = Protection address Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM Ready 0 = WSM Busy
Write C0h Addr=Prot addr
Read
Standby
SR[7] = 1?
Yes
No
Protection Program operations addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program or after a sequence of program operations.
Full Status Check (if desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read SRD Bus Command Operation Standby SR[4:3] =
1,1
Comments SR[1] SR[3] SR[4] 0 1 1 VPP Error 0 0 1 Protection register program error Register locked; Operation aborted
VPP Range Error Standby
SR[4,1] =
1,0
Programming Error
Standby
1
0
1
SR[4,1] =
1,1
Locked-Register Program Aborted
SR[3] MUST be cleared before the WSM will allow further program attempts. Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery.
Program Successful
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 27: Protection Register Locking
0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 PR Lock Register 0 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13.3
VPP Protection
The NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO provides insystem program and erase at VPP1. For factory programming, it also includes a lowcost, backward-compatible 12 V programming feature.(See "Factory Programming" on page 49.) The EFP feature can also be used to greatly improve factory program performance as explained in Section 11.3, "Enhanced Factory Program (EFP)" on page 50. In addition to the flexible block locking, holding the VPP programming voltage low can provide absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or erase operations result in an error displayed in SR[3]. (See Figure 28.)
Figure 28: Examples of VPP Power Supply Configurations
System supply 12 V supply
10K
VCC VPP
System supply Prot# (logic signal)
VCC VPP
* 12 V fast programming * Absolute write protection with V PP VPPLK System supply (Note 1) 12 V supply
* Low-voltage programming * Absolute write protection via logic signal System supply
VCC VPP
VCC VPP
* Low voltage and 12 V fast programming
Note:
* Low-voltage programming
If the VCC supply can sink adequate current, you can use an appropriately valued resistor.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
14.0
Set Configuration Register
The Set Configuration Register command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The configuration register data is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Configuration Register command is written along with the configuration data (on the address bus). This is followed by a second write that confirms the operation and again presents the configuration register data on the address bus. The configuration register data is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the applied VPP voltage. After executing this command, the device returns to read-array mode. The configuration register's contents can be examined by writing the Read Identifier command and then reading location 05h. Undocumented combinations of bits are reserved by Numonyx for future implementations.
Table 25: Configuration Register Definitions
Read Mode RM 15 Res'd R 14 First Access Latency Count LC2 13 LC1 12 LC0 11 WAIT Polarity WT 10 Data Output Config DOC 9 WAIT Config WC 8 Burst Seq BS 7 Clock Config CC 6 Res'd R 5 Res'd R 4 Burst Wrap BW 3 Burst Length BL2 2 BL1 1 BL0 0
Table 26: Configuration Register Descriptions
Bit 15 14 13-11 Name RM (Read Mode) R LC2-0 (First Access Latency Count) WT (WAIT Signal Polarity) DOC (Data Output Configuration) WC (WAIT Configuration) BS (Burst Sequence) CC (Clock Configuration) R R BW (Burst Wrap) Description 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) Reserved 001 = Reserved 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 111 = Reserved (Default) Notes 1 4 6
10 9 8 7 6 5 4 3
0 = WAIT signal is asserted low 1 = WAIT signal is asserted high (Default) 0 = Hold Data for One Clock 1 = Hold Data for Two Clock (Default) 0 = WAIT Asserted During Delay 1 = WAIT Asserted One Data Cycle before Delay (Default) 1 = Linear Burst Order (Default) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge (Default) Reserved Reserved 0 = Wrap bursts within burst length set by CR[2:0] 1 = Don't wrap accesses within burst length set by CR[2:0].(Default) 001 010 011 111 = = = = 4-Word Burst 8-Word Burst 16-Word Burst Continuous Burst (Default)
2 6 6
4 4
2-0
BL2-0 (Burst Length)
3
Notes: 1. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status register and configuration reads support single read cycles. CR[15]=1 disables configuration set by CR[14:0]. 2. Data is not ready when WAIT is asserted. 3. Set the synchronous burst length. In asynchronous page mode, the page size equals four words. 4. Set all reserved configuration register bits to zero. 5. Setting the configuration register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data hold for 2 clocks (RCR.9 = 1), and WAIT asserted one data cycle before delay (RCR8 =1) is not supported.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
14.1
Read Mode (CR[15])
All partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). CR[15] sets the read configuration to one of these modes. Status register, query, and identifier modes support only asynchronous and singlesynchronous read operations.
14.2
First Access Latency Count (CR[13:11])
The First Access Latency Count (CR[13:11]) configuration tells the device how many clocks must elapse from ADV# de-assertion (VIH) before the first data word should be driven onto its data pins. The input clock frequency determines this value. See Table 25, "Configuration Register Definitions" on page 66 for latency values. Figure 29 shows data output latency from ADV# assertion for different latencies. Refer to Section 14.2.1, "Latency Count Settings" on page 68 for Latency Code Settings.
Figure 29: First Access Latency Configuration
CLK [C] Address [A] ADV# [V] D[15:0] [Q] Code 2
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Address
D[15:0] [Q] D[15:0] [Q] D[15:0] [Q]
Code 3 Code 4 Code 5
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Note:
)
Other First Access Latency Configuration settings are reserved.
Figure 30: Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0
1
2
3
4
5
6
7
8
9
A
BCDE
F
16 Word Boundary 4 Word Boundary
The 16-word boundary is the end of the device sense word-line.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
14.2.1
Latency Count Settings
Table 27: Latency Count Setting for VCCQ = 1.7 V - 2.24 V (.13 m lithography)
V CCQ = 1.7 - 2.24 V tAVQV/tCHQV (60 ns/11 ns) Latency Count Settings Frequency Support 2 < 40 3, 4, 5 < 54 MHz Unit
Figure 31: Example: Latency Count Setting at 3
tADD-DELAY CLK (C) CE# (E) ADV# (V) AMAX-0 (A) Code 3 DQ15-0 (D/Q)
High Z Valid Output Valid Output 0st 1nd 2rd 3th
tDATA
4th
Valid Address
R103
14.3
WAIT Signal Polarity (CR[10])
If the WT bit is cleared (CR[10]=0), then WAIT is configured to be asserted low. This means that a 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data. Conversely, if CR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during asynchronous page mode reads.
14.4
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous read array mode (CR[15] is set to 0), and when addressing a partition that is currently in read array mode. In synchronous read array mode, when the device is active (CE# = VIL) and data is valid, CR[10] (WT) determines if WAIT goes to VOH or VOL. The WAIT signal is only deasserted when data is valid on the bus. Invalid data drives the WAIT signal to the asserted state. When the device is operating in synchronous non-array read mode (Read ID, Read Query, Read Status, etc.), the WAIT signal is de-asserted throughout the entire read operation.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
From a system perspective, the WAIT signal is in the asserted state (based on CR[10]) when the device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read Status), or if the device is operating in asynchronous mode (CR[15]=1). In these cases, the system software should ignore (mask) the WAIT signal, because it does not convey any useful information about the validity of what is appearing on the data bus. Table 28: WAIT Signal Conditions
CONDITION WAIT
CE# = VIH CE# = VIL OE# Synchronous Array Read Synchronous Non-Array Read All Asynchronous Read and all Write
Tri-State Active No-Effect Active Asserted Asserted
14.5
Data Hold (CR[9])
The Data Output Configuration bit (CR[9]) determines whether a data word remains valid on the data bus for one or two clock cycles. The processor's minimum data set-up time and the flash memory's clock-to-data output delay determine whether one or two clocks are needed. A Data Output Configuration set at 1-clock data hold corresponds to a 1-clock data cycle; a Data Output Configuration set at 2-clock data hold corresponds to a 2-clock data cycle. The setting of this configuration bit depends on the system and CPU characteristics. For clarification, see Figure 32, "Data Output Configuration with WAIT Signal Delay" on page 70. A method for determining this configuration setting is shown below. To set the device at 1-clock data hold for subsequent reads, the following condition must be satisfied:
tCHQV
(ns) + t DATA
(ns) One CLK Period (ns)
As an example, use a clock frequency of 54 MHz and a clock period of 18.5 ns. Assume the data output hold time is one clock. Apply this data to the formula above for the subsequent reads:
14 ns + 4 ns 18.5 ns
This equation is satisfied, and data output will be available and valid at every clock period. If tDATA is long, hold for two cycles.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 32: Data Output Configuration with WAIT Signal Delay
CLK [C]
WAIT (CR.8 = 1) tCHQV WAIT (CR.8 = 0) Note 1
Valid Output Valid Output Valid Output
Note 1
1 CLK Data Hold
DQ15-0 [Q]
tCHTL/H
WAIT (CR.8 = 0) WAIT (CR.8 = 1)
Note 1 tCHQV Note 1
Valid Output Valid Output
2 CLK Data Hold
DQ15-0 [Q]
Note:
WAIT shown asserted high (CR[10]=1).
14.6
WAIT Delay (CR[8])
The WAIT configuration bit (CR[8]) controls WAIT signal delay behavior for all synchronous read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be asserted either during, or one data cycle before, a valid output. In synchronous linear read array (no-wrap mode CR[3]=1) of 4-, 8-, 16-, or continuous-word burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur. If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT signal informs the system of this delay.
14.7
Burst Sequence (CR[7])
The burst sequence specifies the synchronous-burst mode data order. When operating in a linear burst mode (either 4-, 8-, or 16-word burst length with the burst wrap bit (CR[3]) set, or in continuous burst mode) the device may incur an output delay when the burst sequence crosses the first 16-word boundary, depending on the starting address. If the starting address is aligned to a 4-word boundary, there is no delay. If the starting address is the end of a 4-word boundary, the output delay is one clock cycle less than the First Access Latency Count; this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. The WAIT pin informs the system of this delay.
Table 29: Sequence and Burst Length (Sheet 1 of 2)
Burst Addressing Sequence (Decimal) Start Addr. (Dec) 4-Word Burst
CR[2:0]=001b
8-Word Burst
CR[2:0]=010b
16-Word Burst
CR[2:0]=011b
Continuous Burst
CR[2:0]=111b
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 29: Sequence and Burst Length (Sheet 2 of 2)
0 1 2 Wrap (CR[3]=0) 3 4 5 6 7 ... 14 15 0 1 2 No-Wrap (CR[3]=1) 3 4 5 6 7 ... 14 15 ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... 0-1-2...14-15 1-2-3...14-15-0 2-3-4...15-0-1 3-4-5...15-0-1-2 4-5-6...15-0-1-2-3 5-6-7...15-0-1...4 6-7-8...15-0-1...5 7-8-9...15-0-1...6 ... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ...
14-15-0-1...13 15-0-1-2-3...14 0-1-2...14-15 1-2-3...15-16 2-3-4...16-17 3-4-5...17-18 4-5-6...18-19 5-6-7...19-20 6-7-8...20-21 7-8-9...21-22 ...
14-15-16-17-18-19-20-... 15-16-17-18-19-... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ...
14-15...28-29 15-16...29-30
14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
14.8
Clock Edge (CR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on the clock's rising or falling edge.
14.9
Burst Wrap (CR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst-length boundary or whether they cross word-length boundaries to perform linear accesses. No-wrap mode (CR[3]=1) enables WAIT to hold off the system processor, as it does in the continuous burst mode, until valid data is available. In nowrap mode (CR[3]=0), the device operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-word bursts. For example, if CR[3]=0 (wrap mode) and CR[2:0] = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. If CR[3]=1 (no-wrap mode) and CR[2:0] = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR[3]=1 not only enables limited non-aligned sequential bursts, but also reduces power by minimizing the number of internal read operations.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Setting CR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4word burst sequences. However, significantly more power may be consumed. The 1-23-4 sequence, for example, consumes power during the initial access, again during the internal pipeline lookup as the processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the device pipelines the next 4-word sequence. CR[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess power consumption.
14.10
Burst Length (CR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in synchronous read access of the flash memory array. The burst lengths are 4-word, 8word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 29, "Sequence and Burst Length" on page 70). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the "burstable" address space.
Datasheet 72
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
15.0
Write State Machine States
This table shows the command state transitions based on incoming commands. Only one partition can be actively programming or erasing at a time.
Figure 33: Write State Machine -- Next State Table (Sheet 1 of 2)
C h ip N e x t S ta te a ft e r C o m m a n d In p u t C u r r e n t C h ip S ta te
Ready L o c k /C R S e tu p OTP S e tu p B usy S e tu p P ro g r a m B usy S uspend S e tu p B usy E ra s e S uspend S e tu p P ro g r a m in E ra s e S u s p e n d B usy S uspend L o c k /C R S e tu p in E r a s e S uspend E nhanced F a c to r y P ro g r a m S e tu p EF P Busy E F P V e rify E ra s e S uspend P g m in E ra s e S u s p S e tu p P r o g ra m B u s y P r o g ra m S u s p e n d R e a d y ( E rr o r ) E ra s e B u s y E ra s e S u s p e n d E ra s e B u s y Pgm Busy E ra s e B u s y E ra s e S u s p P r o g ra m B u s y P gm S usp P r o g ra m B u s y P ro g r a m S u s p e n d R e a d y (E r ro r) E ra s e B u s y E ra s e S u s p e n d (8 ) R ead A rr a y
(3 )
P r o g ra m S e tu p
( 4 ,5 )
E ra s e S e tu p
( 4 ,5 )
W r ite S ta te M a c h in e (W S M ) N e x t S ta te T a b le
E nhanced F a c to ry Pgm S e tu p
(4 )
B E C o n firm , P /E R e s u m e , ULB C o n fir m (D 0 H )
(9 )
P r o g ra m / E ra s e S uspend (B 0 H )
Read S ta tu s
C le a r S ta tu s R e g is te r (5 0 H )
(6)
R ead ID /Q u e r y
(F F H ) R eady
(1 0 H /4 0 H ) P r o g ra m S e tu p
(2 0 H ) E ra s e S e tu p
(3 0 H ) EFP S e tu p
(7 0 H ) R eady
(9 0 H , 9 8 H )
R e a d y ( L o c k E r ro r)
Ready O T P Busy
R e a d y (L o c k E rr o r )
P r o g ra m in E r a s e S u s p e n d B u s y P r o g ra m i n E r a s e S u s p e n d B u s y P r o g ra m S u s p e n d in E r a s e S u s p e n d E r a s e S u s p e n d (L o c k E rr o r ) R e a d y ( E rr o r ) P g m in E r a s e S usp B usy E ra s e S u s p E F P B usy EF P Busy
(7 ) (7 )
P g m S u s p in E ra s e S u s p
P ro g r a m in E ra s e S u s p e n d B u s y
P ro g r a m S u s p e n d in E ra s e S u s p e n d E ra s e S u s p e n d (L o c k E rro r) R e a d y (E r ro r)
V e r ify B u s y
O u tp u t N e x t S t a t e a f t e r C o m m a n d In p u t
O u tp u t N e x t S ta te T a b le
P g m S e tu p , E ra s e S e tu p , O T P S e tu p , P g m in E ra s e S u s p S e tu p , E F P S e tu p , E FP B usy, V e r ify B u s y L o c k /C R S e tu p , L o c k /C R S e tu p in E r a s e S u s p O T P Busy Ready, P gm B usy, P gm S uspend, E ra s e B u s y , E ra s e S u s p e n d , P g m In E ra s e S u s p B u s y , P g m S u s p In E r a s e S u s p
(1)
S ta tu s
S ta tu s S ta tu s
A rr a y
(3 )
S ta tu s
O u tp u t d o e s n o t c h a n g e
S ta tu s
O u tp u t does not change
ID /Q u e r y
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 33: Write State Machine -- Next State Table (Sheet 2 of 2)
C h i p N e x t S t a t e a f t e r C o m m a n d In p u t C u r r e n t C h ip S ta te
Ready L o c k /C R S e tu p OTP S e tu p B usy S e tu p P ro g r a m B usy S uspend S e tu p B usy E ra s e S uspend S e tu p P r o g r a m in E ra s e S u s p e n d B usy S uspend L o c k / C R S e t u p in E r a s e S uspend E nhanced F a c to ry P ro g r a m S e tu p EFP Busy E F P V e r if y E FP B usy
(7 ) (7 )
W r it e S t a t e M a c h i n e ( W S M ) N e x t S t a t e T a b l e
(8 )
Lock, U n lo c k , L o c k -d o w n , C R s e tu p (6 0 H ) L o c k /C R S e tu p
(5)
O TP S e tu p
(5 )
Lock B lo c k C o n firm (0 1 H )
(9)
LockD ow n B lo c k C o n f ir m (2 F H )
(9 )
W r it e C R C o n f ir m
(9 )
E nhanced Fact Pgm E x it ( b lk a d d <> W A 0) (X X X X H )
I lle g a l com m ands or E F P d a ta
(2 )
W SM O p e r a t io n C o m p le t e s
(C 0 H ) O TP S e tu p
(0 3 H ) R eady
(o th e r c o d e s )
R e a d y (L o c k E rr o r )
R eady
R eady O TP B usy
R eady
R e a d y ( L o c k E r ro r)
N /A
R eady P ro g ra m B u s y P ro g ra m B u s y P ro g ra m S u s p e n d R e a d y ( E r ro r) E ra s e B u s y L o c k /C R S e t u p in E ra s e S u s p E ra s e S u s p e n d P r o g r a m in E r a s e S u s p e n d B u s y P r o g r a m in E r a s e S u s p e n d B u s y P r o g r a m S u s p e n d in E r a s e S u s p e n d E ra s e S u s p e n d (L o c k E r ro r ) E ra s e S u s p E ra s e S u s p E ra s e S u s p E r a s e S u s p e n d (L o c k E rr o r ) N /A E ra s e S uspend E ra s e B u s y N /A R eady N /A R eady
N /A
R e a d y ( E r ro r) E F P V e r if y R eady E F P B usy E F P V e r if y
(7 ) (7)
V e r if y B u s y
R eady
O u t p u t N e x t S t a t e a f t e r C o m m a n d In p u t
O u t p u t N e x t S t a t e T a b le
P g m S e tu p , E ra s e S e tu p , O T P S e tu p , P g m in E r a s e S u s p S e t u p , E F P S e tu p , EFP Busy, V e r if y B u s y L o c k /C R S e tu p , L o c k / C R S e t u p in E r a s e S u s p O TP Busy Ready, P gm B usy, P gm S uspend, E ra s e B u s y , E ra s e S u s p e n d , P g m In E ra s e S u s p B u s y , P g m S u s p In E ra s e S u s p S ta tu s
(1)
S ta tu s
A r ra y
S ta tu s
O u tp u t d o e s not change
S ta tu s
O u tp u t d o e s n o t c h a n g e
A rr a y
O u tp u t d o e s not change
Notes: 1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the partition's output state. For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every read from partition #4 (without issuing a new command) outputs the Status register. 2. Illegal commands are those not defined in the command set.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
3. 4. 5. 6. 7. 8. 9. 10.
All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in undermined data when a partition address is read. Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to different partitions, the second write determines the active partition. Both partitions will output status information when read. If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Numonyx devices. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend). EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm command. Any other commands are treated as data. The "current state" is that of the WSM, not the partition. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then move to the Ready State. In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block", and "CR Write". In Program suspend or Program suspend in Erase suspend, both cycles of all two cycle commands will be ignored.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
16.0
Common Flash Interface
This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. Software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
16.1
Query Structure Output
The Query database allows software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of wordwide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 30: Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset 00010: Device Addresses 00011: 00012: Hex Code 51 52 59 ASCII Value "Q" "R" "Y"
Table 31: Example of Query Structure Output of x16 Devices (Sheet 1 of 2)
Word Addressing: Offset A[X:0] 00010h 00011h 00012h 00013h 00014h 0051 0052 0059 P IDLO P IDHI Hex Code DQ[15:0] "Q" "R" "Y" PrVendor ID # Value Offset AX - A0 00010h 00011h 00012h 00013h 00014h 0051 0052 0059 P IDLO P IDLO Byte Addressing: Hex Code DQ[7:0] "Q" "R" "Y" PrVendor ID # Value
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 31: Example of Query Structure Output of x16 Devices (Sheet 2 of 2)
Word Addressing: Offset A[X:0] 00015h 00016h 00017h 00018h ... PLO PHI A IDLO A IDHI ... Hex Code DQ[15:0] PrVendor TblAdr AltVendor ID # ... Value Offset AX - A0 00015h 00016h 00017h 00018h ... P IDHI ... Byte Addressing: Hex Code DQ[7:0] ID # ... Value
16.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below.
Table 32: Query Structure
Offset 00000h 00001h (BA+2)h(2) 00004-Fh 00010h 0001Bh 00027h P(3) Description Manufacturer Code Device Code Block Status register Block-specific information Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Vendor-defined additional information specific Primary Intel-specific Extended Query Table to the Primary Vendor Algorithm Sub-Section Name
(1)
Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 32K-word). 3. Offset 15 defines "P" which points to the Primary Numonyx-specific Extended Query Table.
16.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation.
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 33: Block Status Register
Offset Length Description (BA+2)h(1) 1 Block Lock Status Register BSR.0 Block lock status 0 = Unlocked 1 = Locked BSR.1 Block lock-down status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Add. Value BA+2 --00 or --01 BA+2 (bit 0): 0 or 1
BA+2 (bit 1): 0 or 1
BA+2
(bit 2-7): 0
Notes: 1. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 32K-word).
16.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 34: CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --03 14: --00 15: --39 16: --00 17: --00 18: --00 19: --00 1A: --00
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 35: CFI Identification
Offset 1Bh Length 1 Description Hex Add. Code Value 1B: --17 1.7V
1Ch
1
1Dh
1
1Eh
1
1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1D: VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1F: "n" such that typical single word program time-out = 2n -sec 20: "n" such that typical max. buffer write time-out = 2n -sec 21: "n" such that typical block erase time-out = 2n m-sec 22: "n" such that typical full chip erase time-out = 2n m-sec "n" such that maximum word program time-out = 2n times typical 23: 24: "n" such that maximum buffer write time-out = 2n times typical 25: "n" such that maximum block erase time-out = 2n times typical 26: "n" such that maximum chip erase time-out = 2n times typical
--19
1.9V
--B4
11.4V
--C6
12.6V
--04 16s --00 NA --0A 1s --00 NA --04 256s --00 NA --03 8s --00 NA
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
16.5
Device Geometry Definition
Offset 27h Length Description "n" such that device size = 2n in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table:
7 6 5 4 3 2 1 0
Table 36: Device Geometry Definition
Code 27:
See table below
28h
2
--
15
--
14
--
13
--
12
x64
11
x32
10
x16
9
x8
8
28: 29: 2A: 2B: 2C:
--01 --00 --00 --00
x16
2Ah 2Ch
2 1
-- -- -- -- -- -- -- -- "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partit Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information
0
See table below
2Dh
4
31h
4
35h
4
2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
See table below
See table below
See table below
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
32 Mbit -B -T --16 --16 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --3E --00 --00 --20 --00 --00 --01 --07 --3E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
64 Mbit -B -T --17 --17 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --7E --00 --00 --20 --00 --00 --01 --07 --7E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
128 Mbit -B -T --18 --18 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --FE --00 --00 --20 --00 --00 --01 --07 --FE --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
16.6
Numonyx-Specific Extended Query Table
Offset P = 39h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h
(1)
Table 37: Primary Vendor-Specific Extended Query
Length 3 Description (Optional flash features and commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Feature Space supported bit 11 Stepping ID supported (IAS Purposes only) Reserved for internal Intel use (Eas) Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Hex Add. Code Value 39: --50 "P" 3A: --52 "R" 3B: --49 "I" 3C: --31 "1" 3D: --33 "3" --66 3E: 3F: --0B 40: --00 41: --00 bit 0 = 0 No bit 1 = 1 Yes bit 2 = 1 Yes bit 3 = 0 No bit 4 = 0 No bit 5 = 1 Yes bit 6 = 1 Yes bit 7 = 0 No bit 8 = 1 Yes bit 9 = 1 Yes bit 10 = 0 No bit 11 = 1 Yes 42: --01
1 1 4
(P+9)h
1
(P+A)h (P+B)h
2
(P+C)h
1
bit 0 = 1 43: --03 44: --00 bit 0 = 1 bit 1 = 1 45: --18
Yes
Yes Yes 1.8V
(P+D)h
1
46:
--C0
12.0V
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NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 38: Protection Register Information
Offset P = 39h (P+E)h
(1)
Length 1 4
(P+F)h (P+10)h (P+11)h (P+12)h
Hex Description (Optional flash features and commands) Add. Code Value 47: --01 1 Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection fields are available Protection Field 1: Protection Description 48: --80 80h 49: --00 00h This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed 4A: --03 8 byte with device-unique serial numbers. Others are user 4B: --03 8 byte programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits bits bits bits 0-7 = Lock/bytes Jedec-plane physical low address 8-15 = Lock/bytes Jedec-plane physical high address 16-23 = "n" such that 2n = factory pre-programmed bytes 24-31 = "n" such that 2n = user programmable bytes
Table 39: Burst Read Information for A/D-muxed Device
Offset P = 39h (P+13)h
(1)
Length 1
(P+14)h (P+15)h
1 1
(P+16)h (P+17)h
1 1
Description (Optional flash features and commands) Page Mode Read capability bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3-7 = Reserved bits 0-2 "n" such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 4
Hex Add. Code Value 4C: --00 0 byte
4D: 4E:
--03 --01
3 4
4F: 50:
--02 --07
8 Cont
Datasheet 82
November 2007 Order Number: 313272-06
Table 40: Partition and Erase-block Region Information
Offset P = 39h Description Bottom (Optional flash features and commands) Top (P+18)h (P+18)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
(1)
See table below Address Bot Top Len 1 51: 51:
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Partition Region 1 Information
Offset(1) P = 39h Description Bottom Top (Optional flash features and commands) (P+19)h (P+19)h Number of identical partitions within the partition region (P+1A)h (P+1A)h (P+1B)h (P+1B)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1C)h (P+1C)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1E)h (P+1E)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+1F)h (P+1F)h Partition Region 1 Erase Block Type 1 Information (P+20)h (P+20)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+21)h (P+21)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+22)h (P+22)h (P+23)h (P+23)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+24)h (P+24)h (P+25)h (P+25)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+26)h (P+26)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+27)h Partition Region 1 Erase Block Type 2 Information (P+28)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+29)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+2A)h (bottom parameter device only) (P+2B)h Partition 1 (Erase block Type 2) (P+2C)h Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell (P+2D)h bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use Partition 1 (Erase block Type 2) pagemode and synchronous (P+2E)h mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use See table below Address Bot Top Len 2 52: 52: 53: 53: 1 54: 54:
1
55:
55:
1
56:
56:
1
57:
57:
4
2 1
58: 59: 5A: 5B: 5C: 5D: 5E:
58: 59: 5A: 5B: 5C: 5D: 5E:
1
5F:
5F:
4
2 1
60: 61: 62: 63: 64: 65: 66:
1
67:
Datasheet 84
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Partition Region 2 Information
Offset P = 39h Description Bottom (Optional flash features and commands) Top (P+2F)h (P+27)h Number of identical partitions within the partition region (P+30)h (P+28)h (P+31)h (P+29)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+2A)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+33)h (P+2B)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+34)h (P+2C)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+35)h (P+2D)h Partition Region 2 Erase Block Type 1 Information (P+36)h (P+2E)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+37)h (P+2F)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+38)h (P+30)h (P+39)h (P+31)h Partition 2 (Erase block Type 1) (P+3A)h (P+32)h Minimum block erase cycles x 1000 (P+3B)h (P+33)h Partition 2 (Erase block Type 1) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+3C)h (P+34)h Partition 2 (erase block Type 1) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+35)h Partition Region 2 Erase Block Type 2 Information (P+36)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+37)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+38)h (P+39)h Partition 2 (Erase Block Type 2) (P+3A)h Minimum block erase cycles x 1000 (P+3B)h Partition 2 (Erase Block Type 2) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+3C)h Partition 2 (Erase block Type 2) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permit (P+32)h
(1)
See table below Address Bot Top Len 2 68: 60: 69: 61: 1 6A: 62:
1
6B:
63:
1
6C:
64:
1
6D:
65:
4
2 1
6E: 6F: 70: 71: 72: 73: 74:
66: 67: 68: 69: 6A: 6B: 6C:
1
75:
6D:
4
2 1
6E: 6F: 70: 71: 72: 73: 74:
1
75:
November 2007 Order Number: 313272-06
Datasheet 85
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Partition and Erase-block Region Information
Address 51: 52: 53: 54: 55: 56: 57: 58: 59: 5A: 5B: 5C: 5D: 5E: 5F: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 6A: 6B: 6C: 6D: 6E: 6F: 70: 71: 72: 73: 74: 75: 76: 32 Mbit -B -T --02 --02 --01 --07 --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --07 --07 --00 --00 --20 --00 --00 --01 --64 --64 --00 --00 --01 --01 --02 --02 --06 --01 --00 --00 --00 --11 --01 --00 --64 --00 --00 --02 --01 --06 --02 --00 --07 --00 --00 --01 --11 --64 --00 --00 --00 --01 --01 --02 --07 --07 --00 --00 --00 --20 --01 --00 --64 --64 --00 --00 --01 --01 --02 --02 --X --X 64Mbit -B --02 --01 --00 --11 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --02 --06 --00 --00 --01 --64 --00 --01 --02 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --02 --X -T --02 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --02 --01 --00 --11 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --02 --07 --00 --20 --00 --64 --00 --01 --02 --X 128Mbit -B -T --02 --02 --01 --1F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --07 --07 --00 --00 --20 --00 --00 --01 --64 --64 --00 --00 --01 --01 --02 --02 --06 --01 --00 --00 --00 --11 --01 --00 --64 --00 --00 --02 --01 --06 --02 --00 --1F --00 --00 --01 --11 --64 --00 --00 --00 --01 --01 --02 --07 --07 --00 --00 --00 --20 --01 --00 --64 --64 --00 --00 --01 --01 --02 --02 --X --X
X signifies Stepping ID number. See Table C12, above, for more details.
Notes: 1. 2. 3. 4. The variable P is a pointer which is defined at CFI offset 15h. TPD - Top parameter device; BPD - Bottom parameter device. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and parameter blocks. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains all the partitions that are made up of main blocks only. B. contains the partition that is made up of the parameter and the main blocks.
Datasheet 86
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Appendix A Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please contact your local Numonyx representative.
Table 41: 38F Type Stacked Components
PF Package Designator 38F Product Line Designator 5070 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash + RAM Char 3 = RAM die #1 Char 4 = RAM die #2 (See First character applies to Flash die #1 Second character applies to Flash die #2 (See M0 NOR Flash Product Family Y Voltage/NOR Flash CE# Configuration V= 1.8 V Core and I/O; Separate Chip Enable per die (See 0 Parameter / Mux Configuration B Ballout Identifier 0 Device Details
0= No parameter blocks; NonMux I/O interface (See
B= x16D Ballout (See 0= Original released version of this product
Table 43, "38F / 48F Density Decoder" on page 88
for details)
details)
Table 44, "NOR Flash Family Decoder" on page 89 for
details)
Table 45, "Voltage / NOR Flash CE# Configurati on Decoder" on page 89 for
Table 46, "Paramete r / Mux Configurati on Decoder" on page 89 for
details)
Table 4 7, "Ballout Decoder " on page 90
for details)
November 2007 Order Number: 313272-06
Datasheet 87
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 42: 48F Type Stacked Components
PC Package Designator PC = Easy BGA, RoHS RC = Easy BGA, Leaded JS = TSOP, RoHS TE = TSOP, Leaded PF = SCSP, RoHS RD = SCSP, Leaded 48F Product Line Designator 4400 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = Flash die #3 Stacked NOR Flash only Char 4 = Flash die #4 (See First character applies to Flash dies #1 and #2 Second character applies to Flash dies #3 and #4 (See P0 NOR Flash Product Family V Voltage/NOR Flash CE# Configuration B Parameter / Mux Configuration 0 Ballout Identifier 0 Device Details
V= 1.8 V Core and 3 V I/O; Virtual Chip Enable (See
B= Bottom parameter; Non-Mux I/O interface (See
0= Discrete Ballout (See
for details)
Table 43, "38F / 48F Density Decoder" on page 88
details)
Table 44, "NOR Flash Family Decoder" on page 89 for
Table 45, "Voltage / NOR Flash CE# Configurati on Decoder" on page 89 for
details)
Table 46, "Paramete r / Mux Configurati on Decoder" on page 89 for
details)
for details)
Table 4 7, "Ballout Decoder " on page 90
0= Original released version of this product
Table 43: 38F / 48F Density Decoder
Code 0 1 2 3 4 5 6 7 8 9 A B C D E F No Die 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit 128-Gbit 256-Gbit 512-Gbit Flash Density No Die 4-Mbit 8-Mbit 16-Mbit 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit RAM Density
Datasheet 88
November 2007 Order Number: 313272-06
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 44: NOR Flash Family Decoder
Code C C3 J3v.D L18 / L30 M18 P30 / P33 W18 / W30 Family Marketing Name Numonyx Advanced+ Boot Block Flash Memory Numonyx Embedded Flash Memory Numonyx StrataFlash(R) Wireless Memory Numonyx StrataFlash(R) Cellular Memory Numonyx StrataFalsh(R) Embedded Memory Numonyx Wireless Flash Memory No Die
J
L M P W 0(zero)
Table 45: Voltage / NOR Flash CE# Configuration Decoder
Code Z I/O Voltage (Volt) 3.0 1.8 3.0 3.0 1.8 3.0 3.0 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) CE# Configuration Seperate Chip Enable per die Seperate Chip Enable per die Seperate Chip Enable per die Virtual Chip Enable Virtual Chip Enable Virtual Chip Enable Virtual Address Virtual Address Virtual Address
Y
X V U T R Q P
Table 46: Parameter / Mux Configuration Decoder
Code, Mux Identification 0 = Non Mux 1 = AD Mux1 2= AAD Mux 3 =Full" AD Mux2 Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
Any
NA
Notation used for stacks that contain no parameter blocks
1 B = Non Mux C = AD Mux F = "Full" Ad Mux 2 3 4 2 4 X32 X16
Bottom Bottom Bottom Bottom Bottom Bottom
Top Bottom Top Bottom Bottom
Top Bottom Top
Top Top
November 2007 Order Number: 313272-06
Datasheet 89
NumonyxTM Wireless Flash Memory (W18) with AD Multiplexed IO
Table 46: Parameter / Mux Configuration Decoder
Code, Mux Identification Number of Flash Die 1 T = Non Mux U = AD Mux W = "Full" Ad Mux 2 3 4 2 4 X32 X16 Bus Width Flash Die 1 Top Top Top Top Top Top Bottom Top Bottom Top Top Flash Die 2 Bottom Top Bottom Flash Die 3 Bottom Bottom Flash Die 4
1. Only Flash is Muxed and RAM is non-Muxed 2. Both Flash and RAM are AD-Muxed
Table 47: Ballout Decoder
Code 0 (Zero) B C Q U V W SDiscrete ballout (Easay BGA and TSOP) x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus) x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus) QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus) x32SH ballout, 106 ball (x32 NOR only Share Bus) x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus Ballout Definition
Datasheet 90
November 2007 Order Number: 313272-06

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